PPC440EP-3BC400C Applied Micro Circuits Corporation, PPC440EP-3BC400C Datasheet - Page 53

• Manufacturer Part Number: PPC440EP-3BC400C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EP-3BC400C

• Family Name: 440EP
• Device Core: PowerPC
• Device Core Size: 16b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 90C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Lead Free Status / RoHS Status: Not Compliant

Table 8. Signal Functional Description (Sheet 2 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
440EP – PPC440EP Embedded Processor
DDR SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn
DM0:3
DM8
DQS0:3
DQS8
ECC0:7
MemAddr00:12
MemClkOut0
MemClkOut0
MemData00:31
MemSelfRef
RAS
WE
S
S
VREF1
VREF2A:B
Signal Name
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
Clock Enable.
Memory write data byte lane masks. DM8 is the byte lane mask for
the ECC byte lane.
Byte lane data strobe. DQS8 is the data strobe for the ECC byte
lane.
ECC check bits 0:7.
Memory address bus.
Subsystem clock.
Memory data bus.
Self refresh.
Row Address Strobe.
Write Enable.
SSTL reference voltage.
Supplemental SSTL reference voltage.
Description
Revision 1.29 – May 07, 2008
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
Data Sheet
Volt ref receiver
(supplemental)
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
3.3V tolerant
2.5V CMOS
Volt ref pin
Diff driver
Type
Notes
5
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