DSP56857BUE Freescale, DSP56857BUE Datasheet
DSP56857BUE
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DSP56857BUE Summary of contents
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... Data Sheet Technical Data 56800E 16-bit Digital Signal Controllers DSP56857 Rev. 6 01/2007 freescale.com ...
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... SRAM Decoding Peripherals CS0-CS3[3:0] GPIO Contol used as GPIOA0-A3 Freescale Semiconductor • Four (4) dedicated GPIO • 8-bit Parallel Host Interface • General Purpose 16-bit Quad Timer • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Computer Operating Properly (COP)/Watchdog Timer • ...
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... Serial Peripheral Interface (SPI) Port* • Two (2) Enhanced Synchronous Serial Interface (ESSI) modules* • Computer Operating Properly (COP)/Watchdog Timer • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging • Six (6) independent channels of DMA 4 56857 Technical Data, Rev. 6 Freescale Semiconductor ...
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... Host Interface, Two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI), two Serial Communications Interfaces (SCI), and one Quad Timer. The ESSIs, SPI, SCIs IO and Quad Timer can be used as General Purpose Input/Outputs when its primary function is not required. Freescale Semiconductor 56857 Technical Data, Rev. 6 56857 Description ...
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... Product Documentation The four documents listed in Table 1-1 the 56857. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 56857 Chip Documentation Topic ...
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... MODE A, MODE B and MODE C can be used as GPIO after the bootstrap process has completed. 3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ. Freescale Semiconductor each table row describes the package pin and the signal or signals ...
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... SC01 (GPIOC4) SC02 (GPIOC5) STD1 (GPIOD0) SRD1 (GPIOD1) SCK1 (GPIOD2) ESSI 1 SC10 (GPIOD3) SC11 (GPIOD4) SC12 (GPIOD5) MISO (GPIOF0) MOSI (GPIOF1) SPI SCK (GPIOF2) SS (GPIOF3) XTAL PLL / EXTAL Clock CLKO TCK TDI TDO JTAG / Enhanced TMS OnCE TRST DE 2 Freescale Semiconductor ...
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... Freescale Semiconductor Type V Power (V )—These pins provide power to the internal structures of the DD DD chip, and should all be attached Ground (V )—These pins provide grounding for the internal structures the chip and should all be attached to V 56857 Technical Data, Rev. 6 Introduction Description DD. ...
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... V V Ground (V )—These pins provide grounding for all I/O and ESD SSIO SSIO structures of the chip and should all be attached Analog Power (V )—These pins supply an analog power source. DDA DDA 56857 Technical Data, Rev. 6 Description (3.3V) DDIO . (3.3V) DDIO . SS. Freescale Semiconductor ...
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... Input/Output 23 HD1 GPIOB1 Input/Output 24 HD2 GPIOB2 Input/Output Freescale Semiconductor Type V Analog Ground (V SSA SSA External Chip Select (CS0)—This pin is used as a dedicated GPIO. Port A GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. ...
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... Input Host Address (HA0)—This input provides the address selection for HI registers. This pin is disconnected internally. Port B GPIO (8)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. 56857 Technical Data, Rev. 6 Description Freescale Semiconductor ...
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... HWR GPIOB12 Input/Output 84 HCS GPIOB13 Input/Output Freescale Semiconductor Type Input Host Address (HA1)—This input provides the address selection for HI registers. This pin is disconnected internally. Port B GPIO (9)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. ...
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... Timer Input/Output (TIO2)—This pin can be independently configured to be either a timer input source or an output flag. Port G GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. 56857 Technical Data, Rev. 6 Description Freescale Semiconductor ...
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... Output 51 RXD0 GPIOE0 Input/Output Freescale Semiconductor Type Timer Input/Output (TIO3)—This pin can be independently configured to be either a timer input source or an output flag. Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. ...
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... I/O. For synchronous mode, this pin is used either for transmitter1 output or for serial I/O flag 0. Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. 56857 Technical Data, Rev. 6 Description Freescale Semiconductor ...
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... SC10 Input/Output GPIOD3 Input/Output Freescale Semiconductor Type ESSI Serial Control Pin 1 (SC01)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin is the receiver frame sync I/O. For synchronous mode, this pin is used either for transmitter2 output or for serial I/O flag 1. Port C GPIO (4)— ...
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... The driver on this pin can be configured as an open-drain driver by the SPI’s WOM bit when this pin is configured for SPI operation. Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as input or output pin. 56857 Technical Data, Rev. 6 Description Freescale Semiconductor ...
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... TDO Output(Z) 43 TMS Freescale Semiconductor Type SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit rate clock for the SPI. This gated clock signal is an input to a slave device and is generated as an output by a master device. Slave devices ignore the SCK signal unless the SS pin is active low ...
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... Debug Event (DE)—This is an open-drain, bidirectional, active low signal input means of entering debug mode of operation from an external command controller output means of acknowledging that the chip has entered debug mode. This pin is connected internally to a weak pull-up resistor. 56857 Technical Data, Rev. 6 Description . If the design through Freescale Semiconductor ...
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... Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Freescale Semiconductor Table 4-1 are stress ratings only, and functional operation at the CAUTION 56857 Technical Data, Rev. 6 ...
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... SSIO V – 0 0.3 SSA DDA — -40 120 °C -55 150 °C Min Max Unit 1.62 1.98 V 3.0 3.6 V 3.0 3.6 V -40 85 °C — 240 MHz — 120 MHz — 60 MHz — 240 MHz 2 4 MHz — 240 MHz 2 4 MHz Freescale Semiconductor ...
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... Output tri-state current high Output High Voltage Output Low Voltage Output High Current Output Low Current Input capacitance Output capacitance V supply current (Core logic, memories, peripherals Run 2 Deep Stop 3 Light Stop Freescale Semiconductor Table 4-3 Thermal Characteristics Symbol θ I DMAX = 1.62-1.98V 3.0–3.6V ...
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... C = 120MHz Min Typ Max — 1.5 — 60 120 — 2.5 2.85 — 50 — — 1.5 2.0 = 4MHz) into XTAL. All inputs 0.2V from rail; osc 100 120 80 1. and 5. in Table Freescale Semiconductor Unit mA mA μ 4-4) ...
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... V > V > 2.1V) DDIO DD DDIO In practice typically connected directly to V DDA 3.3V Regulator Supply Figure 4-3 Example Circuit to Control Supply Sequencing Freescale Semiconductor and supply, see DDIO to rise as V ramps up. When the V DDIO with some filtering. DDIO 1.8V Regulator 56857 Technical Data, Rev. 6 ...
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... V maximum of 0.8V and Section Low – Data2 Valid Data2 Data Tri-stated Figure 4-5 Signal States 56857 Technical Data, Rev. 6 minimum of 2.0V for IH 4.2. In Figure 4-4 the levels of V High 90% 50% 10% Rise Time and Data3 Valid Data3 Data Active Freescale Semiconductor IH ...
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... Figure 4-7 Connecting a High Speed External Clock Signal using XTAL 4.5.3 Low Speed External Clock Source (2-4MHz) The recommended method of connecting an external clock is given in source is connected to XTAL and the EXTAL pin is held at V set to 0. Freescale Semiconductor Table 4-6. In Figure 4-6 Sample External Crystal Parameters 10MΩ ...
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... PW t — rise t — fall t PW – Figure 4-9 External Clock Timing 56857 Technical Data, Rev ≤ 50pF –40° to +120° 120MHz Typ Max Unit — 240 MHz — — ns — TBD ns — TBD 90% 50% 10 rise fall Freescale Semiconductor ...
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... As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and External Clock period; for an external crystal frequency of 4MHz, ET=250ns. Freescale Semiconductor Table 4-6 PLL Timing = ...
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... Purpose I/O Pin t IG IRQA, IRQB Figure 4-12 External Level-Sensitive Interrupt Timing t IW IRQA Figure 4-13 Recovery from Stop State Using Asynchronous Interrupt Timing RESET IRW b) General Purpose I/O t RSTO Figure 4-14 Reset Output Timing 56857 Technical Data, Rev. 6 Freescale Semiconductor ...
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... Setup time Hold time Setup time Hold time Pulse width Time to re-assert 1. After second write in 16-bit mode 2. After first write in 16-bit mode or after write in 8-bit mode 1. The formulas clock cycle. f ipb = 60MHz 16.7ns. Freescale Semiconductor = 1.62-1.98V 3.0–3.6V DDIO DDA Symbol Min — ...
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... Figure 4-15 Controller-to-Host DMA Read Model HA HCS HDS HRW HD Figure 4-16 Single Strobe Read Mode HA HCS HWR HRD HD 32 TACKDZ TACKDV TREQACKL TACKREQH TRADV TRADV Figure 4-17 Dual Strobe Read Mode 56857 Technical Data, Rev. 6 TACKREQL TRADX TRADZ TRADX TRADZ Freescale Semiconductor ...
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... Figure 4-18 Host-to-Controller DMA Write Mode HA HCS HDS HRW HD Figure 4-19 Single Strobe Write Mode HA HCS HWR HRD HD Freescale Semiconductor TDACKS TREQACKL TACKREQH TWDS TADSS TADSS TWDS TADSS TADSS Figure 4-20 Dual Strobe Write Mode 56857 Technical Data, Rev. 6 Host Interface Port ...
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... Freescale Semiconductor = 120MHz 4-24 4-24 4-24 4-24 4-24 4-24 4-24 4-24 ...
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... SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 4-21 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 4-22 SPI Master Timing (CPHA = 1) Freescale Semiconductor SS is held High on master MSB in Bits 14–1 t ...
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... Figure 4-24 SPI Slave Timing (CPHA = ELD Slave MSB out Bits 14– MSB in Bits 14– ELD Slave MSB out Bits 14– MSB in Bits 14–1 56857 Technical Data, Rev ELG Slave LSB out LSB ELG Slave LSB out t DI LSB in Freescale Semiconductor ...
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... Enhanced Synchronous Serial Interface (ESSI) Timing Table 4-11 ESSI Master Mode Operating Conditions SSIO SSA Parameter SCK frequency 3 SCK period SCK high time SCK low time Output clock rise/fall time Freescale Semiconductor Table 4-10 Quad Timer Timing = 1.62-1.98V 3.0–3.6V DDIO DDA Symbol INHL P ...
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... Freescale Semiconductor ...
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... SS SSIO SSA Parameter SCK frequency 3 SCK period SCK high time SCK low time Output clock rise/fall time Delay from SCK high to SC2 (bl) high - Slave Delay from SCK high to SC2 (wl) high - Slave Freescale Semiconductor t SCKW t SCKL t t TFSBHM TFSBLM TFSWHM t t TXEM ...
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... Technical Data, Rev. 6 ≤ 50pF –40° to +120° 120MHz Min Typ Max Units -1 — — 29 -29 — 29 -29 — 29 -29 — 29 -29 — 29 — — — — — — — — — — — — — 4 — — Freescale Semiconductor ...
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... MHz. MAX 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. Freescale Semiconductor t SCKW t SCKL ...
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... Figure 4-29 TXD Pulse Width Table 4-14 JTAG Timing = 1.62-1.98V 3.0–3.6V DDIO DDA Symbol TRST t DE 56857 Technical Data, Rev ≤ 50pF –40° to +120° 120MHz Min Max Unit DC 30 MHz 33.3 — ns 16.6 — — — ns — — — — ns Freescale Semiconductor ...
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... Figure 4-30 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 4-31 Test Access Port Timing Diagram TRST (Input Figure 4-33 Enhanced OnCE—Debug Event Freescale Semiconductor )/ Input Data Valid TRST Figure 4-32 TRST Timing Diagram DE 56857 Technical Data, Rev ...
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... DDA Symbol INHL P OUT P OUTHL = 120MHz operation and fipb = 60MHz 8.33ns INHL P P OUT OUTHL Figure 4-34 GPIO Timing 56857 Technical Data, Rev ≤ 50pF –40° to +120° 120MHz Min Max Unit — — — — INHL P OUTHL Freescale Semiconductor ...
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... IRQB V DDA V SSA V SSA XTAL EXTAL HD0 HD1 PIN 26 HD2 V DD Figure 5-1 Top View, 56857 100-pin LQFP Package Freescale Semiconductor ORIENTATION MARK 56857 Technical Data, Rev. 6 Package and Pin-Out Information 56857 TXD1 PIN 76 RXD1 V SSIO V DDIO SC12 SC11 SC10 SCK1 ...
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... SSIO CS3 83 HDS V 84 HCS HREQ HACK SS HA0 HA1 HA2 89 V SSIO HRWB 90 V DDIO STD1 91 V SSIO SRD1 92 STD0 SCK1 93 SRD0 SC10 94 SCK0 SC11 95 SC00 SC12 96 SC01 V 97 SC02 DDIO SSIO DDIO RXD1 99 V SSIO TXD1 100 V SSIO Freescale Semiconductor ...
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... S -T- - 0.15 (0.006 -AB- (24X PER SIDE ° 0.25 (0.010 GAUGE PLANE W Q ° DETAIL AD Figure 5-2 100-pin LQPF Mechanical Information Please see www.freescale.com for the most current case outline. Freescale Semiconductor AC T - -AC- G 96X SEATING PLANE 0.100 (0.004 0.20 (0.008) ...
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... θ θJC θCA . For example, the user can change the air flow around θCA – T )/P where 56857 Technical Data, Rev not satisfactorily answer whether θJA is the temperature of the package case T Freescale Semiconductor ...
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... This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V and GND circuits. DD • All inputs must be terminated (i.e., not allowed to float) using CMOS levels. Freescale Semiconductor CAUTION (GND) pin. /V DDA SSA. 56857 Technical Data, Rev. 6 ...
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... The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but requires that TRST be asserted at power on. 50 and V pins. DDA SSA 56857 Technical Data, Rev. 6 Freescale Semiconductor ...
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... Low-Profile Quad Flat Pack (LQFP) DSP56857 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) *This package is RoHS compliant. Freescale Semiconductor Pin Package Type Count 100 100 56857 Technical Data, Rev. 6 Electrical Design Considerations Frequency Order Number (MHz) 120 DSP56857BU120 120 DSP56857BUE * 51 ...
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... Technical Data, Rev. 6 Freescale Semiconductor ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® ...