935285046551 NXP Semiconductors, 935285046551 Datasheet - Page 41

• Manufacturer Part Number: 935285046551
• Manufacturer: NXP Semiconductors

Specifications of 935285046551

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.98V
• Package Type: LQFP
• Screening Level: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System-on-Chip
MEMORY CONTROLLER WAVEFORMS
Static Memory Controller Waveforms
External Static Memory Write, with one Wait State. Fig-
ure 9 shows the waveform and timing for an External
Static Memory Write, with two Wait States. Figure 10
shows the waveform and timing for an External Static
Memory Read, with one Wait State.
by an external device to extend the wait time during a
memory access. The SMC samples nWAIT at the
beginning of at the beginning of each system clock
cycle. The system clock cycle in which the nCSx signal
is asserted counts as the first wait state. See Figure 11.
The SMC recognizes that nWAIT is active within 2
clock cycles after it has been asserted. To assure that
the current access (read or write) will be extended by
nWAIT, program at least two wait states for this bank of
Product data sheet
Figure 8 shows the waveform and timing for an
The SMC supports an nWAIT input that can be used
XTAL32
XTAL14
LREG
nPOR
VDD
PLL
VDDmin
VDDCmin
tLREG
tOSC14
tOSC32
Figure 7. Power-up Stabilization
tPORH
Rev. 02 — 19 March 2009
NXP Semiconductors
memory. If N wait states are programmed, the SMC
holds this state for N system clocks or until the SMC
detects that nWAIT is inactive, whichever occurs last.
As the number of wait states programmed increases,
the amount of delay before nWAIT must be asserted
also increases. If only 2 wait states are programmed,
nWAIT must be asserted in the clock cycle immediately
following the clock cycle during which the nCSx signal
is asserted. Once the SMC detects that the external
device has deactivated nWAIT, the SMC completes its
access in 3 system clock cycles.
ing nCSx and asserting nWAIT is:
measurements are made from the Address Valid point
and HCLK is an internal signal, shown for reference only.
The formula for the allowable delay between assert-
tASSERT = (system clock period) × (Wait States - 1)
(where Wait States is from 2 to 31.)
The signal tIDD is shown without a setup time, as
LH75401/LH75411
LH754xx-100
41