STPCI2HEYCE STMicroelectronics, STPCI2HEYCE Datasheet - Page 40

• Manufacturer Part Number: STPCI2HEYCE
• Manufacturer: STMicroelectronics

Specifications of STPCI2HEYCE

• Lead Free Status / RoHS Status: Compliant

STPC® ATLAS
3.1.3 HCLK PLL STRAP REGISTER
This register is read only.
40/108
1
HCLK_STRAP0
Bit Number Sampled
7
MD[3]
Bits 7-6
Bits 5-3
Bits 2-0
0
0
0
0
RSV
6
This register defaults to the values sampled on the MD pins after reset
MD[2]
0
0
0
0
Mnemonic
MD[26:24]
Rsv
Rsv
MD[26]
Table 3-1. HCLK Frequency Configuration
5
All other settings are reserved
Access = 0022h/0023h
MD[26]
Description
These bits are fixed to ‘0’
These pins reflect the values sampled on MD[26:24] pins respectively
and control the Host clock frequency synthesizer as shown in
Reserved
MD[25]
0
0
0
0
4
MD[24]
MD[25]
3
0
0
1
1
2
MD[24]
0
1
0
1
RSV
1
Regoffset =05Fh
HCLK Speed
25 MHz
50 MHz
60 MHz
66 MHz
Table 3-1
0