STPCC5HEBC STMicroelectronics, STPCC5HEBC Datasheet - Page 22

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STPCC5HEBC

Manufacturer Part Number
STPCC5HEBC
Description
IC SYSTEM-ON-CHIP X86 388-PBGA
Manufacturer
STMicroelectronics
Series
-r
Datasheet

Specifications of STPCC5HEBC

Applications
Set-Top Boxes, TV
Core Processor
x86
Program Memory Type
External Program Memory
Controller Series
STPC® Consumer-II
Ram Size
External
Interface
EBI/EMI, I²C, IDE, ISA, Local Bus
Number Of I /o
-
Voltage - Supply
2.45 V ~ 3.6 V
Operating Temperature
0°C ~ 85°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Not Compliant

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PIN DESCRIPTION
.
22/93
RMRTCCS#
KBCS#
RTCRW#
RTCDS#
SA[19:8]
LA[23]
LA[22]
SA[21]
SA[20]
LA[19:17]
IOCHRDY
BASIC CLOCKS AND RESETS
XTALO
ISA_CLK
ISA_CLK2X
OSC14M
DEV_CLK
HCLK
PCI_CLKO
DCLK
MEMORY CONTROLLER
MCLKO
CS#[3:1]
CS#[0]
MA[10:0], BA[0]
RAS#[1:0], CAS#[1:0]
MWE#, DQM[7:0]
MD[63:0]
PCI INTERFACE
AD[31:0]
CBE[3:0], PAR
FRAME#, TRDY#, IRDY#
STOP#, DEVSEL#
PERR#, SERR#
Table 2-4. ISA / IDE Dynamic Multiplexing
(ISAOE# = 0)
ISA BUS
Signal Name
DD[15]
DD[14]
DD[13]
DD[12]
DD[11:0]
SCS3#
SCS1#
PCS3#
PCS1#
DA[2:0]
DIORDY
(ISAOE# = 1)
IDE
Table 2-6. Signal value on Reset
Release 1.5 - January 29, 2002
14MHz
Low
14MHz
14MHz
24MHz
Oscillating at the speed defined by the strap options.
HCLK divided by 2 or 3, depending on the strap options.
17MHz
66MHz if asynchonous mode, HCLK speed if synchronized mode.
High
High
0x00
High
High
Input
0x0000
Low
Input
Input
Input
SYSRSTI# active
.
SD[15:0]
DREQ_MUX[1:0]
SMEMR#
MEMW#
BHE#
AEN
ALE
MEMR#
IOR#
IOW#
REF#
IOCHCK#
GPIOCS#
ZWS#
SA[7:4]
TC, DACK_ENC[2:0]
SA[3]
ISAOE#,SA[2:0]
DEV_CLK, RTCAS
IOCS16#, MASTER#
SMEMW#, MCS16#
Table 2-5. ISA / Local Bus Pin Sharing
7MHz
SYSRSTI# inactive
SYSRSTO# active
ISA / IPC
SDRAM init sequence:
Write Cycles
First prefetch cycles
when not in Local Bus mode.
PD[15:0]
PA[21:20]
PA[19]
PA[18]
PA[17]
PA[16]
PA[15]
PA[14]
PA[13]
PA[12]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7:4]
PA[3:0]
PRDY
IOCS#[3:0]
FCS#[1:0]
PRD#[1:0]
PWR#[1:0]
release of SYSRSTO#
LOCAL BUS

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