LH79525N0Q100A0,55 NXP Semiconductors, LH79525N0Q100A0,55 Datasheet - Page 29

• Manufacturer Part Number: LH79525N0Q100A0,55
• Manufacturer: NXP Semiconductors

Specifications of LH79525N0Q100A0,55

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: Embedded Control
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.7/3V
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.9/3.6V
• Package Type: LQFP
• Screening Level: Industrial
• Pin Count: 176
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System-on-Chip
AC Test Conditions
Power Consumption By Peripheral Device
individual peripheral device.
Product data sheet
Supply Voltage (VDD)
Core Voltage (VDDC)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Levels
USB Device (+PLL)
Table 13 shows the typical power consumption by
Ethernet Controller
Table 13. Peripheral Current Consumption
Counter/Timers
LCD Controller
PERIPHERAL
ADC/TSC
UARTs
DMA
RTC
SSP
I
PARAMETER
2
S
REFERENCE
SIGNAL (O)
CLOCK
SIGNAL (I)
TYPICAL
5.6 (+3.3)
OUTPUT
INPUT
590
203
670
200
508
203
4.2
2.2
5.1
Figure 9. LH79524/LH79525 Signal Timing
VSS to VDD
3.0 to 3.6
1.7 to 1.9
RATING
VDD/2
2
tOVXXX
Rev. 02 — 17 March 2009
NXP Semiconductors
UNITS
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
UNIT
ns
V
V
V
V
AC Specifications
after a reference clock signal. The illustration in Figure
9 represents all cases of these sets of measurement
parameters; except for the Asynchronous Memory
Interface — which are referenced to Address Valid.
• HCLK, the System Bus clock
• PCLK, the Peripheral Bus clock (locked to HCLK in
• SSPCLK, the Synchronous Serial Interface clock
• UARTCLK, the UART Interface clock
• LCDDCLK, the LCD Data clock from the
• and SDCLK, the SDRAM clock.
point of the clock to the 50% point of the signal. See
Figure 9.
(e.g. tOVA) represents the amount of time for the out-
put to become valid from the rising edge of the refer-
ence clock signal. Maximum requirements for tOVXXX
are shown in Table 14.
amount of time the output will be held valid from the ris-
ing edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 14.
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 14.
amount of time the output must be held valid from the
rising edge of the reference clock signal. Minimum
requirements are shown in Table 14.
tISXXX tIHXXX
the LH79524/LH79525)
LCD Controller
All signals described in Table 14 relate to transitions
The reference clock signals in this design are:
All signal transitions are measured from the 50%
For outputs from the LH79524/LH79525, tOVXXX
The signal tOHXXX (e.g. tOHA) represents the
For Inputs, tISXXX (e.g. tISD) represents the
The signal tIHXXX (e.g. tIHD) represents the
tOHXXX
LH79524/LH79525
LH79525-28
29