MCZ33291EGR2 Freescale, MCZ33291EGR2 Datasheet

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... During Operation DD • Pb-Free Packaging Designated by Suffix Code EG MCU Figure 1. 33291 Simplified Application Schematic Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008. All rights reserved supply. ...

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... Detect From Detectors 1–7 Figure 2. 33291 Simplified Block Diagram = All outputs are latched off while the SPI register is reset PWR Output Gates Outputs 1– 11–14, 23 lLimit + Grounds 5–8, 17–20 has decayed below 26.5 V. PWR Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Short Fault Protect Disable Logic Supply PWR 21 V Output MOSFET Gate Drive Supply 22 RST Reset 23 OP1 Output 1 24 OP0 Output 0 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS OP7 1 24 OP0 OP6 OP1 2 23 SCLK RST VPWR 4 21 GND GND 5 ...

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... Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. ...

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... Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. 14. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 15. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS Symbol R (12) (13) ...

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... V – 1.0 4.0 mA – – 2.5 – 3.5 V – – 2.0 – 0.6 1.2 – 0.55 1.0 – – 3.0 – 1.2 1.6 – 1.0 1.2 A 1.0 2.0 3.0 V 2.5 3.0 3.5 Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... This parameter is guaranteed by design, but it is not production tested. 24. Upper and lower logic threshold voltage levels apply to SI, 25. Hysteresis is characterized, but it is not production tested. 26. Input capacitance SCLK, CS RST tested. 27. Tri-state capacitance of SO for 0 V < V Analog Integrated Circuit Device Data Freescale Semiconductor 5 PWR = BAT A Symbol I OCO DD V ...

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... resistive load. PWR L ) with resistive load. PWR L to 10% Output OFF voltage ( PWR PWR ). PWR 7, page 10. Analog Integrated Circuit Device Data Freescale Semiconductor Unit ...

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... SCLK SI Don't Care 33291 SCLK Under Test C represents the total capacitance of the test fixture and probe. L Figure 5. Valid Data Delay Time and Valid Time Test Circuit Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAM W(SCLKH LEAD W(SCLKL) SI(SU) t SI(HOLD) 0 ...

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... VTri-State 10% t SO(DIS) t SO(DIS) VOH C represents the total capacitance of the test fixture and probe. L VTri-State Figure 10. Output Fault Unlatch Disable PWR 33291 Output Under Test 5 PWR L 33291 Output Under Test Delay Test Circuit Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... DLY(ON) DLY(OFF) times. 2. Turn-OFF is an output programmed from OFF state. 3. Turn- output programmed from and OFF state. Figure 11. Turn-On/-Off Waveforms Analog Integrated Circuit Device Data Freescale Semiconductor t R(SI) < 5 Output Voltage 14 V Waveform ...

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... SPI) is required for chip select to control 32 possible loads. 33291 MOSI SI Shift Register MISO SO SCLK To Logic RST CS ), the maximum output PWR DS(ON) (0.9 typical) and increases to is decreased to 5.5 V. PWR Figure Analog Integrated Circuit Device Data Freescale Semiconductor 14, ...

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... MCU to the other in an orderly manner. The master MCU supplies the system clock signal (top MCU designated the master); the lower MCU being the slave possible to have a system with more than one master; Analog Integrated Circuit Device Data Freescale Semiconductor SCLK CS SCLK SI ...

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... Ports A2 8-Bit SO SCLK 8-Bit SI MISO MOSI V DD 33291 SS CS SCLK MC68XX 8-Bit SO Microcontroller SPI SI (Alternate Master) B0 Parallel A0 33291 Ports SCLK SCLK 8-Bit 8-Bit MISO SO V MOSI Figure 16. Multiple MCU SPI Control 8 Outputs 8 Outputs 8 Outputs Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... CS OFF) is synchronously loaded into the Shift register per the Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL PIN DESCRIPTION data-bit SI state. The Shift register is full after eight bits of information have been entered. To preserve data integrity, care should be taken to not transition SI as SCLK transitions from a low-to-high logic state ...

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... A per output. Each output current PWR of MOSFETs DS(ON) while the Output OFF DS(ON with current DS(ON) and output clamp voltage DS(ON) between outputs of the DS(ON) and clamp voltage of the DS(ON) Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor Figure 18. Data Transfer Timing FUNCTIONAL DESCRIPTION 33291 17 ...

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... The 33291 does not detect an overvoltage on the V pin. Other external circuitry, such as DD the Freescale 33161 Universal Voltage Monitor, is necessary to accomplish this function. OUTPUT OFF OPEN LOAD FAULT An Output OFF Open Load Fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic high state) ...

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... OFF, allowing all remaining outputs to operate normally. Analog Integrated Circuit Device Data Freescale Semiconductor All three protection mechanisms are incorporated in their output, affording robust independent output operation. The analog current limit circuit is always active and monitors the output drain current ...

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... Soft overcurrent faults can condition will result in the global DD goes below the DD is between 5.5 V PWR . Proper operation at V PWR PWR Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... The components R through R represent the steady state thermal resistance of d7 Analog Integrated Circuit Device Data Freescale Semiconductor the silicon die for transistor outputs 0 through 7, while C through C represent the corresponding thermal d7 capacitance of the silicone die translator outputs and plastic. ...

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... R pkg = R leads + R PC Board Ambient Temperature Node R C pkg pkg (C° (F)* (1 1°C Ambient Temperature) 33 0.15 Figure 23 depicts the per output limit Figure 25 illustrates output value is affected by junction Output 6 Output pkg = C flag + C PC Board Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Outputs ON (34°C/W) 0.5 0 -50 - Ambient Temperature (C°) A Figure 24. Maximum SOP Package Steady State Output Current vs. Ambient Temperature Analog Integrated Circuit Device Data Freescale Semiconductor 1.0 @ 150°C=0.8 0.9 T =150°C J 0.8 0.7 0.6 0.5 0.4 0.3 100 125 150 -50 Figure 25 ...

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... PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. 33291 24 PACKAGING PACKAGE DIMENSIONS DW SUFFIX EG SUFFIX PB-FREE) 24-PIN 98ASB42344B ISSUE G Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor DW SUFFIX EG SUFFIX PB-FREE) 24-PIN 98ASB42344B ISSUE G PACKAGING PACKAGE DIMENSIONS 33291 25 ...

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... DESCRIPTION OF CHANGES • Implemented Revision History page 8/2006 3.0 • Converted to Freescale format and prevailing form and style • Added EPP prefix suffix device • Removed MC33291EG/R2 and replaced with MCZ33291EG/R2 in the Ordering Information block • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter 10/2006 4 ...

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... Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...