AM53CF96KC/W AMD (ADVANCED MICRO DEVICES), AM53CF96KC/W Datasheet - Page 41

• Manufacturer Part Number: AM53CF96KC/W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM53CF96KC/W

• Lead Free Status / RoHS Status: Not Compliant

Receive Command Steps Command
(Command Code 2BH/ABH)
The Receive Command Steps Command is used by the
Target to request command information bytes from
the Initiator. During this command the Target receives
the command information bytes from the Initiator
while the SCSI bus is in the Command Phase.
The Target device determines the command block
length from the first byte. If an unknown length is re-
ceived, the Start Transfer Count Register (STCREG) is
loaded with five and the Group Code Valid (GCV) bit in
the Status Register (STATREG) is reset. If a valid length
is received, the STCREG is loaded with the appropriate
value and the GCV bit in the STATREG is set. If ATN sig-
nal is asserted by the Initiator then the Service Request
bit is set in the Interrupt Status Register (INSTREG),
and the Command Register (CMDREG) is cleared. If a
parity error is detected, the command is terminated pre-
maturely and the CMDREG is cleared.
DMA Stop Command (Command Code 04H/84H)
The DMA Stop Command is used by the Target to allow
the microprocessor to discontinue data transfers due to
a lack of activity on the DMA channel. This command is
executed from the top of the command queue. If there is
a queued command waiting execution, it will be over-
written and the Illegal Operation Error (IOE) bit in the
Status Register (STATREG) will be set. This command
is cleared from the command queue once it is decoded.
Caution must be exercised when using this command.
The following conditions must be true:
When conditions are satisfied, the ESC halts, asserts
DREQ, and then waits for the DMA channel. If the ESC
halted during Synchronous Transfer, the ACK pulses
not received from the SCSI bus remain outstanding.
The DMA Stop Command can be used only during
DMA Target Send Data Command or DMA Target
Receive Data Command execution. In both cases
the DMA controller and the ESC must be in the idle
state.
During a DMA Target Send Data Command: the
FIFO is empty or the Current FIFO (CF 4:0) bits in the
Current FIFO/Internal State Register (CFISREG)
are zero.
During a DMA Synchronous Target Receive Data
Command: the Current Transfer Count Register
(CTCREG) is zero, (indicated by the Count to Zero
(CTZ) bit of the Status Register (STATREG)), or the
Synchronous Offset Register (SOFREG) has
reached its maximum value (indicated by the
Synchronous Offset Flag (SOF) bit of the Internal
State Register (ISREG)).
During a DMA Asynchronous Target Receive Data
Command: the FIFO is full (CF 4:0 set to ‘1’ in the
Current FIFO/Internal State Register (CFISREG)),
or Current Transfer Count Register (CTCREG) is
zero (indicated by the Count to Zero (CTZ) bit of the
Status Register (STATREG)).
Am53CF94/Am53CF96
Upon receipt of the DMA Stop Command, the ESC re-
sets the DMA interface and DREQ pin, then terminates
the command in progress. Ongoing SCSI sequences
are completed as follows:
Access FIFO Command (Command Code 05H/85H)
The host may issue the Access FIFO command follow-
ing a Target Abort DMA or abort due to parity error. This
command will give the DMA controller access to the
data remaining in the FIFO. The following shall be true
depending on the status of the DAE bit in CNTRLREG2:
DAE=1:
DREQ will be asserted if the FIFO has two or more bytes
of data, and will deassert if the FIFO contains one or
zero bytes of data.
DAE=0:
DREQ will be asserted if the FIFO is not empty, and will
deassert when the FIFO is empty.
While DREQ is asserted, the DMA controller may read
the data. This command is supported only in normal
DMA mode.
Idle State Commands
The Idle State Commands can be issued to the device
only when the device is disconnected from the SCSI
bus. If these commands are issued to the device when it
is logically connected to the SCSI bus, the commands
are ignored, and the device will generate an Invalid
Command interrupt and clear the Command Register
(CMDREG).
Reselect Steps Command
(Command Code 40H/C0H)
The Reselect Steps Command is used by the Target de-
vice to reselect an Initiator device. When this command
is issued the device arbitrates for the control of the SCSI
bus. If the device wins arbitration, it Reselects the Initia-
tor device and transfers a single byte identify message.
Before issuing this command the SCSI Timeout Regis-
ter (STIMREG), the Control Register One (CNTLREG1)
and the SCSI Destination ID Register (SDIDREG) must
be set to the proper values. If DMA is enabled, the Start
Transfer Count Register (STCREG) must be set to one.
If DMA is not enabled, the single byte identify message
must be loaded into the FIFO before issuing this com-
mand. This command will be terminated early if the
SCSI Timeout Register times out, or if sequence termi-
nates normally, a Successful Operation interrupt will be
issued. This command also resets the Internal State
Register (ISREG).
Synch Data Send: completes when CTZ bit in Status
Register is ‘1’.
Synch Data Receive: when all outstanding ACKs
received, command completes
Asynchronous Data Send: immediately completes
Asynchronous Data Receive: immediately com-
pletes. Remaining data in FIFO should be removed
by microprocessor.
AMD
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