ISP1160BD-S NXP Semiconductors, ISP1160BD-S Datasheet - Page 40

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ISP1160BD-S

Manufacturer Part Number
ISP1160BD-S
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1160BD-S

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Table 14.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInteruptStatus register: bit allocation
10.1.5 HcInterruptEnable register (R/W: 04H/84H)
reserved
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 15.
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. A hardware interrupt is requested on the host
bus when three conditions occur:
Bit
31 to 7
6
5
4
3
2
1
0
RHSC
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
HcInterruptStatus register: bit description
Symbol
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 07 — 29 September 2009
Description
reserved
RootHubStatusChange: This bit is set when the content of
HcRhStatus or the content of any of HcRhPortStatus[1:2] has
changed.
FrameNumberOverflow: This bit is set when the MSB of
HcFmNumber (bit 15) changes value.
UnrecoverableError: This bit is set when the HC detects a system
error not related to USB. The HC does not proceed with any
processing nor signaling before the system error has been corrected.
The HCD clears this bit after the HC has been reset. OHCI: Always set
to logic 0.
ResumeDetected: This bit is set when the HC detects that a device
on the USB is asserting resume signaling from a state of no resume
signaling. This bit is not set when HCD enters the USBResume state.
StartOfFrame: At the start of each frame, this bit is set by the HC and
an SOF generated.
reserved
SchedulingOverrun: This bit is set when USB schedules for current
frame overruns. A scheduling overrun will also cause the
SchedulingOverrunCount of HcCommandStatus to be incremented.
R/W
R/W
R/W
R/W
UE
28
20
12
0
0
0
4
0
reserved
reserved
reserved
R/W
R/W
R/W
R/W
RD
27
19
11
0
0
0
3
0
Embedded USB host controller
R/W
R/W
R/W
R/W
SF
26
18
10
0
0
0
2
0
ISP1160/01
reserved
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
R/W
R/W
R/W
R/W
SO
24
16
0
0
8
0
0
0
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