ISP1581BD NXP Semiconductors, ISP1581BD Datasheet - Page 30

• Manufacturer Part Number: ISP1581BD
• Manufacturer: NXP Semiconductors

Specifications of ISP1581BD

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 13462
Product data
UDMA read/write (opcode = 02H/03H) — Ultra DMA mode for IDE transfers; the
specification of this mode can be obtained from the ATA Specification Rev. 4 . Pins
DA0 to DA2, CS0 and CS1 are used to select a device register for access. Control
signals are mapped as follows: DREQ (= DMARQ), DACK (= DMACK), DIOW
(= STOP), DIOR (= HDMARDY or HSTROBE), IORDY (= DSTROBE or DDMARDY).
Table 26:
Table 27:
Control bits
GDMA read/write (opcode = 00H/01H)
DMA Configuration register (see
BURST[2:0]
MODE[1:0]
WIDTH0
DIS_XFER_CNT
ATA_MODE
DMA Hardware register (see
EOT_POL
ENDIAN[1:0]
ACK_POL, DREQ_POL,
WRITE_POL, READ_POL
MASTER
MDMA (Master) read/write (opcode = 06H/07H)
DMA Configuration register (see
DMA_MODE[1:0]
MODE[1:0]
WIDTH
DIS_XFER_CNT
ATA_MODE
DMA Hardware register (see
EOT_POL
ENDIAN[1:0]
ACK_POL, DREQ_POL,
WRITE_POL, READ_POL
MASTER
Control bits
PIO read/write (opcode = 04H/05H)
DMA Configuration register (see
PIO_MODE[2:0]
ATA_MODE
Control bits for Generic DMA transfers
Control bits for IDE-specified DMA transfers
Rev. 06 — 23 December 2004
Table 35
Table 35
Table 33
Table 33
Table 33
Description
determines the number of DMA cycles, during which pin
DREQ is kept asserted
determines the active read/write data strobe signals
selects the DMA bus width: 8 or 16 bits
disables the use of the DMA Transfer Counter
set to logic 0 (non-ATA transfer)
selects the polarity of the EOT signal
determines whether the data is to be byte swapped or
normal. Applicable only in 16 bit mode.
select the polarity of the DMA handshake signals
set to logic 0 (slave)
determines the MDMA timings for the DIOR and DIOW
strobes (value 03H is used for UDMA only)
determines the active data strobe(s).
selects the DMA bus width: 8 or 16 bits
disables the use of the DMA Transfer Counter
set to logic 1 (ATA transfer)
input EOT is not used
determines whether the data is to be byte swapped or
normal. Applicable only in 16 bit mode.
select the polarity of the DMA handshake signals
set to logic 1 (master)
Description
selects the PIO mode; timings are ATA(PI) compatible
set to logic 1 (ATA transfer)
and
and
and
and
and
Table
Table
Table
Table
Table
36)
36)
Hi-Speed USB peripheral controller
34)
34)
34)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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