CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 10

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Signal Definitions
2.2.2
2.2.3
Signal Name
SCLK
SDIN
SDO
SCS
Signal Name
SHFCLK
UD[11:0]
LD[11:0]
LDE
LP
HSYNC
Serial Interface Signals
Flat Panel Interface Signals
Pin No.
Pin No.
15, 16,
20:29
3:14
40
41
42
43
30
32
31
(Continued)
(Drive)
(Drive)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
Type
Type
mA)
(12
O
O
O
O
O
I
I
I
Description
Serial Interface Clock
This input signal is the clock for the serial control interface. Data is clocked in
and out on the rising edge. The other serial interface signals (SDIN, SCS,
and SDO) are synchronous to this signal.
Serial Data Input
This is the data input line for the serial control interface. Input data is serial-
ized on this pin, including the command stream for register reads and writes.
Serial Data Output
This is the data output line for the serial control interface. Output data is seri-
alized on this pin in response to register read commands.
Serial Chip Select
This active high chip select indicates when valid data is being clocked in or
out via the SDIN/SDO pins.
Offset
404h[25] = 1
Offset
404h[26] = 0
404h[26] = 1
Offset
Selection
Function
---
---
10
Description
Panel Clock (Shift Clock)
This is the shift clock or pixel clock for the flat panel data.
This signal is used to clock pixel data into the LCD panel.
Depending on the type of panel being interfaced, this signal
can also be referred to as CL2 or SHIFT.
Upper and Lower Scan Data
These outputs are the panel pixel data bus to the LCD
panel. The data format is dependent on the panel type
selected. Refer to Section 3.2.2 “Mode Selection” on page
19.
Flat Panel Display Enable (TFT Panels)
LDE is the display enable for active-matrix TFT panels and
is used to indicate the active pixel data on UD[11:0] and
LD[11:0].
Latch Pulse (SSTN/DSTN Panels)
Latch Pulse is the line pulse or latch pulse for the flat panel
data, indicating that a display line is about to start.
Depending on the type of panel being interfaced, this signal
can also be referred to as CL1 or LINE.
Horizontal Sync (TFT Panels)
HSYNC is the horizontal sync for the active-matrix TFT
panel. This is a delayed version of the input HSYNC signal
with the appropriate pipeline delay relative to the pixel data
on UD[11:0] and LD[11:0].
If pin 31 is set as HSYNC at Offset 404h[26], its polarity is
programmable through Offset 404h[22]:
0 = Active high; 1 = Active low.
Revision 2.1