CDP68HC68P1E Intersil, CDP68HC68P1E Datasheet - Page 7

• Manufacturer Part Number: CDP68HC68P1E
• Manufacturer: Intersil

Specifications of CDP68HC68P1E

• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant

Addressing the Single Port I/O
The Serial Peripheral Interface (SPI) utilized by the I/O Port
is a serial synchronous bus for control and data transfers. It
consists of a SCK clock input pin that shifts data out of the
I/O port (MISO, MASTER IN, SLAVE OUT) and latches data
presented at the input pin, MOSI (master out, slave in). Data
is transferred most significant bit first. There is one SCK
clock for each bit transferred and bits are transferred in
groups of eight.
When the I/O port is selected by bringing the chip enable pin
low, the logic level at the SCK input is sampled to determine
the internal latching and shift polarity for input and output
signals on the SPI. (See Figure 3).
The first byte shifted in when the chip is selected is always
the control byte followed by one or more bytes that become
data or a mask for the data and data direction register. As
the control byte is being shifted in one the MOSI line, data on
the MOSI line shifts out. (See Figure 4).
C07 (ID
C05 (RS) - Register Select. When RS is low, the data
register is selected. When RS is high, the Direction Register
is selected.
ID1
7
1
), C06 (ID
ID0
6
RS
X = DON’T CARE
Z = HIGH IMPEDANCE
*
Z = HIGH IMPEDANCE
*
5
0
= COMPARE FLAG
= COMPARE FLAG
MOSI
MISO
MOSI
MISO
): Chip-Identify bits.
CE
CE
R/W
4
Z
Z
7
DF1
3
D0 - D7
MOSI
SCK
C07
C07
Z
Z
DF0
2
C06
C06
Z
Z
FIGURE 9. PORT-PIN DATA CHANGES
CM1
1
C05
C07
C05
C07
FIGURE 7. READ BYTES
FIGURE 8. READ BYTES
CDP68HC68P1
CM0
D3
0
C06
C06
0
1
PREVIOUS
C03
C05
C03
C05
D2
C02
C02
C04 (R/W) - Read/Write. Low when data is to be
transferred from the SPI I/O to the CPU (read) and high
when the I/O is receiving data from the CPU (write).
C03 (DF1), C02 (DF0) - Data Format Bits. These have
meaning only when R/W is high. During a write operation,
DF1 and DF0 control how the byte following the control word
is interpreted. See Data Format.
C01 (CM1), C00 (CM0) - Compare Mode Select. These
bits select one of four events which will set the internal
Condition Flag. See Compare Operation.
Read Operation
During a read operation, the CPU transfers data from the I/O
by first sending a control byte on the MOSI line while the
chip-selected I/O sends compare information followed by
one or more data bytes on the MISO line. The selected
register will be continuously read if CE is held low after the
first data byte is shifted out.
Write Operation
During a write operation, the data byte follows the control
byte for the selected register. While this byte is being shifted
in, old data from that register is shifted out. If CE remains low
after the data byte is shifted in, MISO becomes high
impedance and the new data is placed in the selected
register. At the time the eighth data bit is strobed into the
data pins (D0 - D7) will change as indicated in Figure 7-9.
0
1
D1
C01
C03
C01
C03
D0
C00
C00
*
*
PREVIOUS 8-BIT WORD
NEW
X
8-BIT DATA WORD
8-BIT DATA WORD
X
X
X X X X X