USB2228-NU-09 Standard Microsystems (SMSC), USB2228-NU-09 Datasheet - Page 10

• Manufacturer Part Number: USB2228-NU-09
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB2228-NU-09

• Lead Free Status / RoHS Status: Compliant

4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs
Datasheet
Chapter 5 Pin Descriptions
SMSC USB2227/USB2228
5.1
CF_D[15:8]
SYMBOL
CF_nCS1
CF_nCS0
CF_SA2
CF_SA1
CF_SA0
CF_IRQ
This section provides a detailed description of each signal. The signals are arranged in functional
groups according to their associated interface.
The “n” symbol in the signal name indicates that the active, or asserted state occurs when the signal
is at a low voltage level. When “n” is not present before the signal name, the signal is asserted when
at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working
with a mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a
signal is active, independent of whether that level is represented by a high or low voltage. The term
negate, or negation indicates that a signal is inactive.
PIN Descriptions
128-PIN
VTQFP
61
60
64
63
62
55
52
51
50
48
46
45
41
40
CompactFlash (In True IDE mode) INTERFACE
BUFFER
I/O8PD
O8PU
TYPE
O8PU
IPD
O8
O8
O8
DATASHEET
CF Chip Select 1:
This pin is the active low chip select 1 signal for the CF ATA
device.
CF Chip Select 0:
This pin is the active low chip select 0 signal for the task file
registers of CF ATA device in the True IDE mode.
CF Register Address 2:
This pin is the register select address bit 2 for the CF ATA
device.
CF Register Address 1:
This pin is the register select address bit 1 for the CF ATA
device.
CF Register Address 0:
This pin is the register select address bit 0 for the CF ATA
device.
CF Interrupt:
This is the active high interrupt request signal from the CF
device.
CF Data 15-8:
The bi-directional data signals CF_D15-CF_D8 in True IDE
mode data transfer.
In the True IDE Mode, all of task file register operation occur on
the CF_D[7:0], while the data transfer is on CF_D[15:0].
The bi-directional data signal has an internal weak pull-down
resistor.
10
DESCRIPTION
Revision 1.93 (11-01-07)