ISP1160BM/01 STEricsson, ISP1160BM/01 Datasheet - Page 23

• Manufacturer Part Number: ISP1160BM/01
• Manufacturer: STEricsson

Specifications of ISP1160BM/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1160-01_7
Product data sheet
9.4.2 Data organization
PTD data is used for every data transfer between a microprocessor and the USB bus, and
the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the payload data
is placed just after the PTD, after which the next PTD is placed. For an IN transfer, RAM
space is reserved for receiving a number of bytes that is equal to the total bytes of the
transfer. After this, the next PTD and its payload data are placed (see
Remark: The PTD is defined for both the ATL and ITL type data transfer. For ITL, the PTD
data is put into ITL buffer RAM, and the ISP1160/01 takes care of the Ping-Pong action for
the ITL buffer RAM access.
The PTD data (PTD header and its payload data) is a structure of DWORD alignment.
This means that the memory address is organized in blocks of 4 bytes. Therefore, the first
byte of every PTD and the first byte of every payload data are located at an address that is
a multiple of 4.
long, meaning that the last byte of the payload data is at the location 15H. The next
addresses (16H and 17H) are not multiples of 4. Therefore, the first byte of the next PTD
will be located at the next multiple-of-four address (18H).
Fig 18. Buffer RAM data organization.
Figure 19
Rev. 07 — 29 September 2009
illustrates an example in which the first payload data is 14 bytes
bottom
top
payload data of OUT transfer
empty space for IN total data
payload data of OUT transfer
PTD of OUT transfer
PTD of OUT transfer
PTD of IN transfer
RAM buffer
MGT952
Embedded USB host controller
000H
7FFH
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
Figure
18).
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