USB2227-NU-11 Standard Microsystems (SMSC), USB2227-NU-11 Datasheet - Page 16

• Manufacturer Part Number: USB2227-NU-11
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB2227-NU-11

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs
Datasheet
SMSC USB2227/USB2228
MA[1:0]/CLK_S
SYMBOL
EL[1:0]
nMWR
GPIO1
GPIO2
GPIO3
nMRD
nMCE
128-PIN
VTQFP
117
116
114
113
14
13
17
94
BUFFER
I/O8PD
TYPE
I/O8
I/O8
I/O8
O8
O8
O8
DATASHEET
Memory Address Bus:
MA[1:0], These signals address memory locations within the
external memory.
SEL[1:0]. During nRESET assertion, these pins will select the
operating frequency of the external clock, and the
corresponding weak pull-down resistors are enabled. When
nRESET is negated, the value on these pins will be internal
latched and these pins will revert to MA[1:0] functionality, the
internal pull-downs will be disabled.
SEL[1:0] = ‘00’. 24MHz
SEL[1:0] = ‘01’. RESERVED
SEL[1:0] = ‘10’. RESERVED
SEL[1:0] = ‘11’. 48MHz
Note:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
If the latched value is ‘0’, then the corresponding MA pin will
function identically to the MA[15:3] pins at all times (other than
during nRESET assertion).
Memory Write Strobe:
Program Memory Write; active low
Memory Read Strobe:
Program Memory Read; active low
Memory Chip Enable:
Program Memory Chip Enable; active low.
This signal is asserted, when any of the following conditions are
no longer met:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
Note:
General Purpose I/O:
This pin may be used either as input, edge sensitive interrupt
input, or output.
General Purpose I/O:
This pin may be used either as input, edge sensitive interrupt
input, or output.
General Purpose I/O:
This pin may be used either as input, edge sensitive interrupt
input, or output.
MISC
16
If the latched value is ‘1’, then the corresponding MA
pin is tri-stated when the following conditions are true:
This signal is held to a logic ‘high’ while nRESET is
asserted.
DESCRIPTION
Revision 1.93 (11-01-07)