ISP1181ADGG STEricsson, ISP1181ADGG Datasheet - Page 37

• Manufacturer Part Number: ISP1181ADGG
• Manufacturer: STEricsson

Specifications of ISP1181ADGG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Table 35:
9397 750 13959
Product data
Bit
Symbol
Reset
Access
Error Code Register: bit allocation
UNREAD
R
7
0
12.2.7 Acknowledge Setup
12.3.1 Read Endpoint Error Code
12.3 General commands
Table 34:
This command acknowledges to the host that a SETUP packet was received. The
arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands
for the control IN and OUT endpoints. The microcontroller needs to re-enable these
commands by sending an Acknowledge Setup command, see
Code (Hex): F4 — acknowledge setup
Transaction — none
This command returns the status of the last transaction of the selected endpoint, as
stored in the Error Code Register. Each new transaction overwrites the previous
status information. The bit allocation of the Error Code Register is shown in
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 byte
Table 36:
DATA01
Bit
3
2
1
0
Bit
7
6
R
6
0
Endpoint Status Image Register: bit description
Error Code Register: bit description
Symbol
OVERWRITE
SETUPT
CPUBUF
-
Symbol
UNREAD
DATA01
reserved
R
5
0
Rev. 05 — 08 December 2004
Description
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
reserved
Description
A logic 1 indicates that a new event occurred before the
previous status was read.
This bit indicates the PID type of the last successfully received
or transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).
R
4
0
R
3
0
ERROR[3:0]
Full-speed USB peripheral controller
R
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
…continued
Section
ISP1181A
R
1
0
9.5.
Table
RTOK
R
0
0
36 of 70
35.