CP82C37A-5 Intersil, CP82C37A-5 Datasheet - Page 12

• Manufacturer Part Number: CP82C37A-5
• Manufacturer: Intersil

Specifications of CP82C37A-5

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

External EOP Operation
The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up
resistor to V
resistor used should guarantee a rise time of less than
125ns. It is important to note that the 82C37A will not accept
Application Information
Figure 6 shows an application for a DMA system utilizing the
82C37A DMA controller and the 80C88 Microprocessor. In
this application, the 82C37A DMA controller is used to
improve system performance by allowing an I/O device to
transfer data directly to or from system memory.
Components
The system clock is generated by the 82C84A clock driver
and is inverted to meet the clock high and low times required
by the 82C37A DMA controller. The four OR gates are used
to support the 80C88 Microprocessor in minimum mode by
producing the control signals used by the processor to
access memory or I/O. A decoder is used to generate chip
CHANNEL
0
1
2
3
CC
Base and Current Address
Current Address
Base and Current Word
Count
Current Word Count
Base and Current Address
Current Address
Base and Current Word
Count
Current Word Count
Base and Current Address
Current Address
Base and Current Word
Count
Current Word Count
Base and Current Address
Current Address
Base and Current Word
Count
Current Word Count
is required. The value of the external pull-up
REGISTER
12
FIGURE 5. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
Read
Write
Read
OPERATION
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
0
0
0
0
0
0
CS
82C37A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
IOR
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
external EOP signals when it is in a SI (Idle) state. The
controller must be active to latch EXT EOP. Once latched,
the EXT EOP will be acted upon during the next S2 state,
unless the 82C37A enters an idle state first. In the latter
case, the latched EOP is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C37A is in an SI state.
select for the DMA controller and memory. The most
significant bits of the address are output on the address/data
bus. Therefore, the 82C82 octal latch is used to demultiplex
the address. Hold Acknowledge (HLDA) and Address
Enable (AEN) are “ORed” together to insure that the DMA
controller does not have bus contention with the
microprocessor.
Operation
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold
Acknowledge signal is returned to the DMA controller from
the 80C88 processor. After the Hold Acknowledge has been
IOW
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
SIGNALS
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
FIRST/LAST
FLIP-FLOP
STATE
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
1
DATA BUS
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
DB0-DB7
March 20, 2006
FN2967.2