PDIUSBD12PWTM STEricsson, PDIUSBD12PWTM Datasheet - Page 15

• Manufacturer Part Number: PDIUSBD12PWTM
• Manufacturer: STEricsson

Specifications of PDIUSBD12PWTM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CD00222704
Product data sheet
11.2.4.1 DMA Configuration register
11.2.4 Set DMA
Table 6.
Code (Hex) — FB
Transaction — read or write 1 B
The Set DMA command is followed by one data write or read to or from the DMA
Configuration register.
During the DMA operation, the 2 B buffer header (status and byte length information) is
not transferred to or from the local CPU. This allows the DMA data to be continuous and
not interleaved by chunks of these headers. For DMA read operations, the header will be
skipped by the PDIUSBD12. See
header will be automatically added by the PDIUSBD12. This provides a clean and simple
DMA data transfer.
Bit
7
6
3 to 0 CLOCK DIVISION
Fig 8.
Symbol
SOF-ONLY
INTERRUPT MODE
SET_TO_ONE
FACTOR
For bit allocation, see
Set DMA command: bit allocation
Set Mode command, clock division factor byte: bit allocation
7 6 5 4 3 2
0 0
0 0
Rev. 12 — 8 April 2010
Table
Description
Setting this bit to logic 1 will cause the interrupt line to be activated
because of the Start-Of-Frame (SOF) clock only, regardless of the
setting of PIN-INTERRUPT MODE, bit 5 of Set DMA.
operation. This bit should always be set to logic 1 after power. It is
zero after power-on reset.
The value indicates the clock division factor for CLKOUT. The
output frequency is 48 MHz / (N + 1), where N is the clock division
factor. The reset value is 11. This will produce an output frequency
of 4 MHz that can then be programmed up or down by the user.
The minimum value is 1, giving a frequency range of
4 MHz to 24 MHz. The minimum value of N is 0, giving a maximum
frequency of 48 MHz. The maximum value of N is 11, giving a
minimum frequency of 4 MHz. The PDIUSBD12 design ensures no
glitching during frequency change. The programmed value will not
be changed by a bus reset.
This bit must be set to logic 1 before any DMA read or DMA write
0 0
7.
Section 11.3.5
1
0
0
0
Power-on value
DMA BURST
DMA ENABLE
DMA DIRECTION
AUTO RELOAD
INTERRUPT PIN MODE
ENDPOINT INDEX 4 INTERRUPT ENABLE
ENDPOINT INDEX 5 INTERRUPT ENABLE
USB peripheral controller with parallel bus
command. For DMA write operations, the
PDIUSBD12
004aaa801
© ST-ERICSSON 2010. All rights reserved.
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