WP413812 S LAMU Intel, WP413812 S LAMU Datasheet - Page 26

• Manufacturer Part Number: WP413812 S LAMU
• Manufacturer: Intel

Specifications of WP413812 S LAMU

• Lead Free Status / RoHS Status: Compliant

T a b l e 9 .
I n t e l
D a t a s h e e t
2 6
®
4 1 3 8 0 8 a n d I n t e l
U A R T S i g n a l s ( S h e e t 2 o f 2 )
U1_TXD
U1_CTS#
U1_RTS#
T o t a l
®
N a m e
4 1 3 8 1 2 S A S / S A T A I / O C o n t r o l l e r s i n T P E R M o d e
C o u n t
1
1
1
8
ActLow
ActLow
Async
Async
Async
T y p e
O
O
I
UART 1 Serial Output: Composite serial data output to the
communications link-peripheral, modem, or data set. The TXD
signal is set to the MARKING (logic 1) state upon a reset operation.
UART 1 Clear to Send: When low, this pin indicates that the
receiving UART is ready to receive data. When the receiving UART
deasserts CTS# high, the transmitting UART must stop
transmission to prevent overflow of the receiving UART buffer. The
CTS# signal is a modem-status input whose condition can be tested
by the host processor or by the UART when in Autoflow Mode as
described below:
Non-Autoflow Mode:
NOTE: When UART transmission is stalled by disabling the UART,
Autoflow Mode:
NOTE: In Autoflow Mode, the UART transmit circuity checks the
UART 1 Request to Send: This bit indicates to the remote device
whether the UART is ready to receive data. When low, the UART is
ready to receive data. A reset operation sets this signal to its
inactive (high) state. LOOP Mode operation holds this signal in its
inactive state.
Non-Autoflow Mode:
Autoflow Mode:
When not in Autoflow Mode, bit[4] (CTS) of the Modem Status
The RTS# output signal can be asserted by setting bit[1] (RTS)
RTS# is automatically asserted by the autoflow circuitry when
Register (MSR) indicates the state of CTS#. Bit[4] is the
complement of the CTS# signal. Bit[0] (DCTS) of the Modem
Status Register indicates whether the CTS# input has changed
state since the previous reading of the Modem Status Register.
CTS# has no effect on the transmitter. The user can program
the UART to interrupt the processor when DCTS changes
state. The programmer can then stall the outgoing datastream
by starving the transmit FIFO or disabling the UART with the
IER register.
of the Modem Control Register to 1. The RTS bit is the
complement of the RTS# signal.
the receive buffer exceeds its programmed threshold. It is
deasserted when enough bytes are removed from the buffer to
lower the data level back to the threshold.
the user does not receive an MSR interrupt when CTS#
reasserts. This is because disabling the UART also disables
interrupts. To get around this, the user can use Auto CTS in
Autoflow Mode, or program the CTS# pin to interrupt.
state of CTS# before transmitting each byte. When CTS# is
high, no data is transmitted.
I n t e l
®
4 1 3 8 0 8 a n d 4 1 3 8 1 2 — P a c k a g e I n f o r m a t i o n
D e s c r i p t i o n
O r d e r N u m b e r : 3 1 7 8 0 6 - 0 0 1 U S
O c t o b e r 2 0 0 7