PLR135/T7 Everlight Electronics CO., LTD, PLR135/T7 Datasheet - Page 8

• Manufacturer Part Number: PLR135/T7
• Description: Photodetector Transistors Photo Link
• Manufacturer: Everlight Electronics CO., LTD

Specifications of PLR135/T7

• Optical Fiber Type: RX
• Data Transfer Rate: 16Mbps
• Optical Rise Time: 20ns
• Optical Fall Time: 20ns
• Jitter: 5ns
• Operating Temperature Classification: Commercial
• Peak Wavelength: 650nm
• Operating Supply Voltage (min): 2.4V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -20C to 70C
• Mounting: Snap in
• Pin Count: 5
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

guidelines must be followed. These guidelines ensure the most reliable PLR135 POF performance
for the motherboard integration. Failed to implement these PCB guidelines may affect the PLR135
jitter and low input power performances.
1. Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size
2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance
3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes
EVERLIGHT ELECTRONICS CO., LTD.
Office: No 25, Lane 76, Sec 3, Chung Yang Rd,
Tucheng, Taipei 236, Taiwan, R.O.C
Everlight Electronics Co., Ltd.
Device NO: DPL-135-012
805 or smaller) capacitor as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf
act as a low impedance path to ground for any stray high frequency transient noises.
formed by an isolated Vcc and Gnd planes is critical. The POF device must be mounted directly
on these two planes to reduce the lead parasitic inductance.
at a single point using ferrite beads. The beads are used to block the high frequency noises from
the digital planes while still allowing the DC connections between the planes
To achieve better jitter and low input optical power performances, several PCB layout
Application Notes: PLR135 Series PCB layout for motherboard integration
Prepared Date:07-25-2005
http://www.everlight.com
Fax: [phone]
Tel: [phone]
http://www.everlight.com
Rev 2
Prepared By: Chin-Chia Hsu
PLR135/T7
Page: 8 of 8