MCIMX27LMOP4A Freescale, MCIMX27LMOP4A Datasheet - Page 64

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MCIMX27LMOP4A

Manufacturer Part Number
MCIMX27LMOP4A
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX27LMOP4A

Lead Free Status / RoHS Status
Compliant

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Electrical Characteristics
64
1
Note:
VSYNC
HSYNC
HSYNC
LSCLK
T is pixel clock period.
OE
LD
T1
T2
T3
T4
T5
T6
T1
T2
T3
T4
T5
T6
ID
ID
Delay from the end of HSYNC to the beginning of the OE pulse.
Pixel Clock period
LP width
LD setup time
LD hold time
Wait between LP and FLM rising edge
Wait between last data and LP rising edge
Delay from end of OE to the beginning of the HSYNC pulse.
T2
Line 1
T5
Line 2
Table 31. LCDC Non-TFT Mode Timing Parameters
T3
T1
Table 32. LCDC TFT Mode Timing Parameters
Figure 27. LCDC TFT Mode Timing Diagram
Pixel Clock period
T4
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
HSYNC width
LD setup time
LD hold time
Description
Description
Line n
22.5
22.5
Min
Min
1
5
5
3
1
1
5
5
2
1
Line 1
Freescale Semiconductor
1000
1000
Max
Ma
T6
Unit
Unit
ns
ns
ns
T
T
T
ns
T
ns
ns
T
T
1
1
1
1
1
1

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