LM1971MX/HAPB National Semiconductor, LM1971MX/HAPB Datasheet - Page 6

• Manufacturer Part Number: LM1971MX/HAPB
• Manufacturer: National Semiconductor

Specifications of LM1971MX/HAPB

• Lead Free Status / RoHS Status: Not Compliant

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Typical Performance Characteristics
Application Information
SERIAL DATA FORMAT
The LM1971 uses a 3-wire serial communication format that
is easily controlled by a microcontroller. The timing for the
3-wire set, comprised of DATA, CLOCK, and LOAD is shown
in Figure 2. As depicted in Figure 2, the LOAD line is to go
low at least 150 ns before the rising edge of the first clock
pulse and is to remain low throughout the transmission of the
16 data bits. The serial data is composed of an 8-bit address,
which must always be set to 0000 0000 to select the single
audio channel, and 8 bits for attenuation setting. For both
address data and attenuation setting data, the MSB is sent
first with the address data preceding the attenuation data.
Please refer to Figure 3 to confirm the serial data format
transfer process.
Table 1 shows the various Address and Data byte values for
different attenuation settings. Note that Address bytes other
than 0000 0000 are ignored.
µPOT SYSTEM ARCHITECTURE
The µPot’s digital interface is essentially a shift register
where serial data is shifted in, latched, and then decoded.
Once new data is shifted in, the LOAD line goes high,
latching in the new data. The data is then decoded and the
appropriate switch is activated to set the desired attenuation
level. This process is continued each and every time an
attenuation change is made. When the µPot is powered up,
it is placed into the Mute mode.
µPOT DIGITAL COMPATIBILITY
The µPot’s digital interface section is compatible with TTL or
CMOS logic. The shift register inputs act upon a threshold of
two diode drops above the ground level (Pin 3) or approxi-
mately 1.4V.
THD vs Freq by FFT
01235320
6
(Continued)
TABLE 1. Attenuator Register Set Description
0000 0000
0000 0001
0000 0010
0000 0000
0000 0001
0000 0010
0001 0000
0001 0001
0001 0010
0100 0000
0000 0011
0001 0011
0011 1101
MSB LSB
MSB LSB
0011 1110
0011 1111
Contents
1111 1110
1111 1111
D7–D0
A7–A0
:::::
:::::
:::::
Address Register (Byte 0)
Output Impedance vs
Data Register (Byte 1)
Attenuation Level
Attenuation (dB)
Channel 1
96 (Mute)
96 (Mute)
96 (Mute)
96 (Mute)
Ignored
Ignored
16.0
17.0
18.0
19.0
61.0
62.0
0.0
1.0
2.0
3.0
::
::
::
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