PI3VDP411LSZDE Pericom Semiconductor, PI3VDP411LSZDE Datasheet - Page 4

• Manufacturer Part Number: PI3VDP411LSZDE
• Manufacturer: Pericom Semiconductor

Specifications of PI3VDP411LSZDE

• Lead Free Status / RoHS Status: Compliant

Pin Name
OUT_D2+
OUT_D2–
OUT_D1+
OUT_D1–
HPD_SINK
HPD_SOURCE
SCL_SOURCE
SDA_SOURCE
SCL_SINK
SDA_SINK
DDC_EN
VDD
OC_2
(REXT)
08-0294
Type
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
5V tolerance single-ended input Low Frequency, 0V to 5V (nominal) input signal. This
3.3V single-ended output
Single-ended 3.3V open-drain
DDC I/O
Single-ended 3.3V open-drain
DDC I/O
Single-ended 5V open-drain
DDC I/O
Single-ended 5V open-drain
DDC I/O
5.0V tolerant Single-ended input Enables bias voltage to the DDC passgate level shifter
3.3V DC Supply
3.3V single-ended control input
4
Description
HDMI 1.3 compliant TMDS output. OUT_D2+ makes
a differential output signal with OUT_D2–.
HDMI 1.3 compliant TMDS output. OUT_D2– makes
a differential output signal with OUT_D2+.
HDMI 1.3 compliant TMDS output. OUT_D1+ makes
a differential output signal with OUT_D1–.
HDMI 1.3 compliant TMDS output. OUT_D1– makes
a differential output signal with OUT_D1+.
signal comes from the HDMI connector. Voltage High
indicates "plugged" state; voltage low indicated
"unplugged". HPD_SINK is pulled down by an
integrated 100K ohm put-down resistor.
HPD_SOURCE: 0V to 3.3V (nominal) output signal.
This is level-shifted version of the HPD_SINK signal.
3.3V DDC Data I/O. Pulled up by external termina-
tion to 3.3V. Connected to SCL_SINK through volt-
age-limiting integrated NMOS passgate.
3.3V DDC Data I/O. Pulled up by external termination
to 3.3V. Connected to SDA_SINK through voltage-
limiting integrated NMOS passgate.
5V DDC Clock I/O. Pulled up by external termination
to 5V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS passgate.
5V DDC Data I/O. Pulled up by external termination
to 5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS passgate.
gates. (May be implemented as a bias voltage connec-
tion to the DDC pass gates themselves.)
3.3V ± 10%
Acceptable connections to OC_1 (REXT) pin are: Re-
sistor to GND; Resistor to 3.3V; NC. (Resistor should
be 0-ohm).
DDC_EN
0V
3.3V
digital video input to a DVI/HDMI transmitter
Digital Video Level Shifter from AC coupled
Passgate
Disabled
Enabled
PI3VDP411LS
PS8913D
11/05/08