ADV7400AKSTZ-80 Analog Devices Inc, ADV7400AKSTZ-80 Datasheet - Page 12

• Manufacturer Part Number: ADV7400AKSTZ-80
• Manufacturer: Analog Devices Inc

Specifications of ADV7400AKSTZ-80

• Lead Free Status / RoHS Status: Compliant

ADV7400A
DETAILED DESCRIPTION
ANALOG FRONT END
The ADV7400A analog front end includes three 10-bit ADCs,
which digitize the analog video signal before applying it to the
SDP or CP (see Table 8 for sampling rates). The analog front
end uses differential channels to each ADC to ensure high
performance in a mixed-signal application.
The front end also includes a 12-channel input mux, which
enables multiple video signals to be applied to the ADV7400A.
Current and voltage clamps are positioned in front of each ADC
to ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping either in the CP or SDP.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
anti-aliasing filters. This has the benefit of an increased signal-
to-noise ratio (SNR).
Table 8. Maximum ADC Sampling Rates
Model
ADV7400AKSTZ-80
ADV7400AKSTZ-110
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of
baseband video signals in composite and S-video formats. The
video standards supported by the SDP include PAL B/D/I/G/H,
PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and
SECAM B/D/G/K/L. The ADV7400A can automatically detect
the video standard and process it accordingly.
The SDP has a 5-line super adaptive 2D comb filter that gives
superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
The SDP has an IF filter block that compensates for attenuation
in the high frequency luma spectrum due to tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
Max ADC Sampling Rate
80 MHz
110 MHz
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The ADV7400A implements a patented adaptive-digital-line-
length-tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7400A to track and decode poor quality video sources
such as VCRs, noisy sources from tuner outputs, VCD players,
and camcorders. The SDP contains a chroma transient
improvement (CTI) processor. This processor increases the
edge rate on chroma transitions, resulting in a sharper video
image.
The SDP can process a variety of VBI data services, such as
closed captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), EDTV, Gemstar
1×/2×, and extended data service (XDS). The ADV7400A SDP
section has a Macrovision 7.1 detection circuit, which allows it
to detect Types I, II, and III protection levels. The decoder is
fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range
of component video formats in any color space. Component
video standards supported by the CP are 525i, 625i, 525p, 625p,
720p, 1080i, 1250i, VGA up to SXGA @ 60 Hz, and many other
standards not listed here.
The CP section of the ADV7400A also contains an automatic
gain control (AGC) block. In cases where no embedded sync is
present, the video gain can be set manually. The AGC block is
followed by a digital clamp circuit that ensures the video signal
is clamped to the correct blanking level. Automatic adjustments
within the CP include gain (contrast) and offset (brightness);
manual adjustment controls are also supported.
A fully programmable any-to-any 3 × 3 color space conversion
matrix is placed between the analog front end and the CP
section. This enables YPrPb to RGB and RGB to YCrCb conver-
sions. Many other standards of color space may be implemented
using the color space converter.
The output section of the CP is highly flexible. It can be config-
ured in single data rate mode (SDR) with one data packet per
clock cycle or in a double data rate (DDR) mode where data is
presented on the rising and falling edge of the clock. In SDR
mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these
modes HS, VS, and FIELD/DE (where applicable) timing refer-
ence signals are provided. In DDR mode, the ADV7400A can be
configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb
pixel output interface with corresponding timing signals.