CY7C019V-20AC Cypress Semiconductor Corp, CY7C019V-20AC Datasheet - Page 2

• Manufacturer Part Number: CY7C019V-20AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C019V-20AC

• Density: 1.125Mb
• Access Time (max): 20ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 175mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 9b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06044 Rev. *C
Functional Description
The CY7C008V/009V and CY7018V/019V are low-power
CMOS 64K, 128K x 8/9 dual-port static RAMs. Various
arbitration schemes are included on the devices to handle
situations when multiple processors access the same piece of
data. Two ports are provided permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as standalone 8/9-bit
dual-port static RAMs or multiple devices can be combined in
order to function as a 16/18-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for implementing 16/18-bit
or wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
communications
video/graphics memory.
Pin Configurations
Note:
4. This pin is NC for CY7C008V.
[4]
SEML
CE0L
CE1L
R/WL
A10L
A12L
A13L
A14L
A15L
A16L
A11L
GND
VCC
OEL
A7L
A8L
A9L
NC
NC
NC
NC
NC
NC
NC
NC
status
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
26
buffering,
99
27
98
28
97
29
96
30
95
31
and
94
32
CY7C009V (128K x 8)
CY7C008V (64K x 8)
93
33
92 91 90
34 35 36
dual-port
100-Pin TQFP
(Top View)
89
37
88
38
87 86
39 40
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is
controlled independently on each port by a chip select (CE)
pin.
The CY7C008V/009V and CY7018V/019V are available in
100-pin Thin Quad Plastic Flatpacks (TQFP).
85
41
84
42
83 82 81
43 44 45
80
46
79
47
78 77
48 49
76
50
CY7C008V/009V
CY7C018V/019V
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R
GND
NC
NC
NC
NC
CE0R
CE1R
SEMR
R/WR
OER
GND
GND
NC
[4]
Page 2 of 18
[+] Feedback