CY7C146-55JC Cypress Semiconductor Corp, CY7C146-55JC Datasheet - Page 5

• Manufacturer Part Number: CY7C146-55JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C146-55JC

• Density: 16Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 22b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 110mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 52
• Word Size: 8b
• Number Of Words: 2K
• Lead Free Status / RoHS Status: Not Compliant

Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30)
Notes
Document #: 38-06031 Rev. *E
13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
14. CY7C142/CY7C146 only.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
16. 52-pin PLCC and PQFP versions only.
Write Cycle
t
t
t
t
t
t
t
t
t
t
Busy/Interrupt Timing
t
t
t
t
t
t
t
t
t
t
Interrupt Timing
t
t
t
t
t
t
Shaded areas contain preliminary information.
12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
DDD
WDD
WINS
EINS
INS
OINR
EINR
INR
Parameter
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
[12]
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
R/W Pulse Width
Data Setup to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset Time
Address to INTERRUPT Reset Time
[16]
Description
[7]
[7]
[13]
[14]
[13]
[13]
[8]
(continued)
[13]
[13]
Min
7C136-15
15
12
12
12
10
13
2
0
0
0
5
0
7C146-15
Note 15
Note 15
Max
10
15
15
15
15
15
15
15
15
15
15
15
[4]
CY7C136A, CY7C142, CY7C146
Min
7C132-25
25
20
20
15
15
20
2
0
0
0
5
0
7C136-25
7C142-25
7C146-25
Note 15
Note 15
Max
15
20
20
20
20
25
25
25
25
25
25
25
[4]
CY7C132, CY7C136
Min
30
25
25
25
15
30
2
0
0
0
5
0
7C132-30
7C136-30
7C142-30
7C146-30
Note 15
Note 15
Max
15
20
20
20
20
30
25
25
25
25
25
25
Page 5 of 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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