IDT71256S100DB IDT, Integrated Device Technology Inc, IDT71256S100DB Datasheet - Page 8

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IDT71256S100DB

Manufacturer Part Number
IDT71256S100DB
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71256S100DB

Density
256Kb
Access Time (max)
100ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
15b
Package Type
CDIP
Operating Temp Range
-55C to 125C
Number Of Ports
1
Supply Current
135mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Military
Mounting
Through Hole
Pin Count
28
Word Size
8b
Number Of Words
32K
Lead Free Status / RoHS Status
Not Compliant

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Company
Part Number
Manufacturer
Quantity
Price
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INTERSIL
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Part Number:
IDT71256S100DB
Manufacturer:
IDT
Quantity:
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Part Number:
IDT71256S100DB
Manufacturer:
IDT
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Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. t
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
ADDRESS
ADDRESS
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
DATA
DATA
on the bus for the required t
as the specified t
WR
DATA
is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
WE
CS
OUT
WE
OE
IN
CS
IN
WP
. For a CS controlled write cycle, OE may be LOW with no degradation to t
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short
t
t
AS
AS
(3)
t
WZ
(5)
t
t
AW
AW
t
WP
t
t
CW
WC
t
(6)
WC
(6)
8
Military, Commercial, and Industrial Temperature Ranges
WP
t
DW
t
or (t
DW
CW
WHZ
.
+t
DW
) to allow the I/O drivers to turn off and data to be placed
t
DH
t
WR
t
t
WR
t
OW
t
DH2
(1,2,4)
(1,2,4,6)
t
OHZ
(5)
(3)
2946 drw 10
2946 drw 11

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