GS8160Z18BT-150I GSI TECHNOLOGY, GS8160Z18BT-150I Datasheet

GS8160Z18BT-150I

Manufacturer Part Number

GS8160Z18BT-150I

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS8160Z18BT-150I.pdf (23 pages)

Specifications of GS8160Z18BT-150I

Density

18Mb

Access Time (max)

7.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

133MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

20b

Package Type

TQFP

Operating Temp Range

-40C to 85C

Number Of Ports

Supply Current

185mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

100

Word Size

18b

Number Of Words

Lead Free Status / RoHS Status

Not Compliant

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS8160Z18/36BT is an 18Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.06 9/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Flow Through

Pipeline

3-1-1-1

2-1-1-1

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

Curr

tCycle

Parameter Synopsis

(x18)

(x36)

(x18)

(x36)

1/23

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8160Z18/36BT may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

The GS8160Z18/36BT is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

-250

295

345

225

255

2.5

4.0

5.5

-200

245

285

200

220

3.0

5.0

6.5

-150

200

225

185

205

3.8

6.7

7.5

GS8160Z18/36BT-250/200/150

Unit

250 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS8160Z18BT-150I

GS8160Z18BT-150I Summary of contents

Page 1

... Curr (x36) t 5.5 6.5 KQ 5.5 6.5 tCycle 225 200 Curr (x18) 255 220 Curr (x36) 1/23 GS8160Z18/36BT-250/200/150 250 MHz–150 MHz 3.3 V I/O -150 Unit 3.8 ns 6.7 ns 200 mA 225 mA 7.5 ns 7.5 ns 185 mA 205 mA © 2004, GSI Technology DD ...

Page 2

... B DQP DDQ Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.06 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36BT-250/200/150 GS8160Z18BT Pinout Top View 2/ DDQ DQP ...

Page 3

... V 4 DDQ DDQ DDQ DDQ DQP Rev: 1.06 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36BT-250/200/150 GS8160Z36BT Pinout 512K x 36 Top View 3/23 DQP DDQ DDQ DDQ DDQ DQP 51 A © 2004, GSI Technology ...

Page 4

... Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply 4/23 ; active low A ; active low B ; active low C ; active low D © 2004, GSI Technology ...

Page 5

... GS8160Z18/36B NBT SRAM Functional Block Diagram Rev: 1.06 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18/36BT-250/200/150 Amps Sense Drivers Write 5/23 © 2004, GSI Technology ...

Page 6

... Rev: 1.06 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com & determine which bytes will be written. All or none may be activated 6/23 GS8160Z18/36BT-250/200/150 , E and E ). Deassertion of any one of the Enable 2 3 © 2004, GSI Technology ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. External L Next L External L Next L External L External L Next L Next L None L None L None L None L None Current L 7/23 GS8160Z18/36BT-250/200/150 High High High-Z 1,2,3, High High High High High © 2004, GSI Technology Notes 1,10 2 1,2,10 3 2,3 1,3, ...

Page 8

... and D represent input command codes ,as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipeline and Flow Through Read/Write Control State Diagram 8/23 GS8160Z18/36BT-250/200/150 New Write Burst Write B D n+3 ƒ ƒ © 2004, GSI Technology ...

Page 9

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 9/23 GS8160Z18/36BT-250/200/150 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2004, GSI Technology ...

Page 10

... Pipeline and Flow Through Read Write Control State Diagram 10/23 GS8160Z18/36BT-250/200/150 R B Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2004, GSI Technology ...

Page 11

... Note: The burst counter wraps to initial state on the 5th clock. 11/23 GS8160Z18/36BT-250/200/150 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2004, GSI Technology ...

Page 12

... Rev: 1.06 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH DD 12/23 GS8160Z18/36BT-250/200/150 2. The duration of SB tZZR pipelined parts and V on flow DDQ SS © 2004, GSI Technology ...

Page 13

... V maximum, with a pulse width not to exceed 50% tKC. DDn 13/23 GS8160Z18/36BT-250/200/150 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 DDQ –0 +0.5 DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2004, GSI Technology Unit Notes ...

Page 14

... A T – +1.5 V maximum, with a pulse width not to exceed 50% tKC. DDn 14/23 GS8160Z18/36BT-250/200/150 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2004, GSI Technology ...

Page 15

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 15/23 GS8160Z18/36BT-250/200/150 50% tKC DD IL Typ. Max. Unit 30pF © 2004, GSI Technology ...

Page 16

... IN I Output Disable OUT –8 mA, V OH2 OH DDQ –8 mA, V OH3 OH DDQ 16/23 GS8160Z18/36BT-250/200/150 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – 2.375 V 1 3.135 V 2.4 V — © 2004, GSI Technology Max — — 0.4 V ...

Page 17

... DD3 DD2 DDQ3 DDQ2 17/23 GS8160Z18/36BT-250/200/150 -200 -150 –40 0 –40 0 – 85°C 70°C 85°C 70°C 85°C 315 255 265 205 215 245 205 215 190 200 285 230 240 185 195 225 190 200 175 185 © 2004, GSI Technology Unit ...

Page 18

... GSI Technology ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Pipeline Mode Timing (NBT) Suspend Read C Write D Suspend1 tKH tKH tKC tKC tKL tKL tKQ tH tS tKQ D(A) Q(B) Q(C) 19/23 GS8160Z18/36BT-250/200/150 Write Read E Deselect tKQ tHZ tKQX tLZ tKQX D(D) Q(E) © 2004, GSI Technology ...

Page 20

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Flow Through Mode Timing (NBT) Suspend Read C Write D1 Suspend1 tKL tKL tKC tKC tHZ tKQ tKQX Q(B) Q(C) 20/23 GS8160Z18/36BT-250/200/150 Write Read E Deselect E tHZ tLZ tKQX D(D) Q(E) © 2004, GSI Technology ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 21/23 GS8160Z18/36BT-250/200/150 E1 E BPR 1999.05.18 © 2004, GSI Technology ...

Page 22

... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS8160Z18BT-250 GS8160Z18BT-200 GS8160Z18BT-150 512K x 36 GS8160Z36BT-250 512K x 36 GS8160Z36BT-200 512K x 36 GS8160Z36BT-150 GS8160Z18BT-250I GS8160Z18BT-200I GS8160Z18BT-150I 512K x 36 GS8160Z36BT-250I 512K x 36 GS8160Z36BT-200I 512K x 36 GS8160Z36BT-150I GS8160Z18BGT-250 GS8160Z18BGT-200 GS8160Z18BGT-150 512K x 36 GS8160Z36BGT-250 512K x 36 GS8160Z36BGT-200 512K x 36 GS8160Z36BGT-150 GS8160Z18BGT-250I ...

Page 23

... Removed 300 MHz speed bin Content • Changed Pb-Free to RoHS-compliant • Added Status column to Ordering Information table • Corrected pin description table Content • Added missing Abs Max section • Updated for MP status Content 23/23 GS8160Z18/36BT-250/200/150 © 2004, GSI Technology ...

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