CY7C09359AV-9AC Cypress Semiconductor Corp, CY7C09359AV-9AC Datasheet
CY7C09359AV-9AC
Specifications of CY7C09359AV-9AC
Related parts for CY7C09359AV-9AC
CY7C09359AV-9AC Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — organization (CY7C09349AV) — organization (CY7C09359AV) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 83-MHz operation • ...
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... Functional Description The CY7C09349AV and CY7C09359AV are high-speed 3.3V synchronous CMOS 4K and dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, and data lines allow for minimal set- up and hold times. In pipelined output mode, data is registered for decreased cycle time ...
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... Typical Standby Current for I (mA) (Both Ports TTL Level) SB1 Typical Standby Current for (Both Ports CMOS Level) SB3 Shaded areas contain advance information. Note: 3. This pin is NC for CY7C09349AV. 100-Pin TQFP (Top View CY7C09359AV (8K x 18) CY7C09349AV ( CY7C09349AV CY7C09359AV A8R ...
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... Storage Temperature ................................. – +150 C Ambient Temperature with Power Applied .............................................– +125 C Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................–0. Input Voltage......................................–0. Notes: 4. Industrial parts are available in CY7C09359AV only. Description –A for 4K, A –A for 8K devices ...
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... Ind. Com’l. – 0.2V [4] Ind. Com’ [4] MAX Ind. Test Conditions MHz 3.3V CC AND CE must be asserted to their active states ( CY7C09349AV CY7C09359AV CY7C09349AV CY7C09359AV -9 -12 Typ. Max. Min. Typ. Max. Unit 2.4 V 0.4 0.4 V 2.0 V 0.8 0 – 135 230 115 180 ...
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... AC Test Loads 3. 590 OUTPUT 435 (a) Normal Load (Load 250 TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) 6 CY7C09349AV CY7C09359AV 3. 590 OUTPUT 435 (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) [+] Feedback ...
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... Data Output Hold After Clock HIGH DC t Clock HIGH to Output High Z CKHZ t Clock HIGH to Output Low Z CKLZ Port to Port Delays t Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-up Time CCS CY7C09349AV CY7C09359AV CY7C09349AV CY7C09359AV -9 -12 Min. Max. Min ...
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... n+1 t OHZ [ CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only CY7C09349AV CY7C09359AV n+3 t CKHZ Q n OLZ n n+1 n+2 t OHZ t OLZ t OE [+] Feedback ...
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... CD1 CWDD CD2 HC CD2 SC CKHZ CKLZ [12, 13, 14, 15] NO MATCH t CD1 NO MATCH t CWDD VALID . for the left port, which is being written to CY7C09349AV CY7C09359AV CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 VALID >maximum specified, then data is not valid CWDD CCS D 4 [+] Feedback ...
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... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. [9, 16, 17, 18 n+1 n CD2 CKHZ OPERATION [9, 16, 17, 18 n+1 n+2 n n+2 n+3 t CD2 OHZ WRITE . IH 10 CY7C09349AV CY7C09359AV A A n+3 n CD2 CKLZ Q n+3 WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ [+] Feedback ...
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... DATA IN t CD1 Q n DATA OUT OE [7, 9, 17, 18 n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [7, 9, 16, 17, 18 n+1 n+2 n n+2 n OHZ READ WRITE 11 CY7C09349AV CY7C09359AV n+3 n CD1 CD1 Q n CKLZ DC WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ DC READ [+] Feedback ...
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... SAD t t SCN t CD2 n+1 COUNTER HOLD READ WITH COUNTER [19 n+1 COUNTER HOLD READ WITH COUNTER . IH 12 CY7C09349AV CY7C09359AV HAD HCN Q Q n+2 n+3 READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+2 n+3 READ WITH COUNTER [+] Feedback ...
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... CNTRST = 21. The “Internal Address” is equal to the “External Address” when ADS = V [20, 21 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = CY7C09349AV CY7C09359AV n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . IH [+] Feedback ...
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... SRST HRST CNTRST t SD DATA DATA OUT COUNTER RESET Notes: 22 UB, and 23. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 14 CY7C09349AV CY7C09359AV n n READ READ ADDRESS [+] Feedback ...
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... CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09349AV CY7C09359AV Operation [27] Deselected [27] Deselected Write [27] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation [+] Feedback ...
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... A100 100-Pin Thin Quad Flat Pack Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack CY7C09349AV CY7C09359AV Operating Range Commercial Commercial Operating Range Commercial Commercial Industrial 51-85048-B [+] Feedback ...