CY7C09389V-12AC Cypress Semiconductor Corp, CY7C09389V-12AC Datasheet - Page 8

• Manufacturer Part Number: CY7C09389V-12AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09389V-12AC

• Density: 1.125Mb
• Access Time (max): 25ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 33MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Number Of Words: 64K
• Lead Free Status / RoHS Status: Not Compliant

Switching Waveforms
Notes
Document #: 38-06056 Rev. *C
17. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
18. ADS = V
19. The output is disabled (high impedance state) by CE
20. Addresses do not have to be accessed sequentially since ADS = V
ADDRESS
ADDRESS
DATA
DATA
IL
CLK
R/W
CLK
R/W
, CNTEN and CNTRST = V
CE
CE
CE
CE
OUT
OUT
OE
OE
0
1
0
1
t
t
t
t
t
t
SC
SW
SA
SC
SW
SA
Figure 5. Read Cycle for Flow Through Output (FT/PIPE = V
A
A
Figure 6. Read Cycle for Pipelined Operation (FT/PIPE = V
n
n
t
t
t
t
t
t
t
HC
HW
HA
t
HC
HW
HA
IH
CH1
t
CH2
CKLZ
1 Latency
.
t
CD1
t
t
CYC1
CYC2
t
CKLZ
0
t
t
CL1
CL2
=V
IH
or CE
A
A
n+1
n+1
1
t
Q
DC
= V
IL
n
t
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
CD2
IL
following the next rising edge of the clock.
Q
A
A
n
n+2
n+2
Q
t
OHZ
n+1
t
DC
IH
IL
)
)
[17, 18, 19, 20]
t
t
Q
[17, 18, 19, 20]
SC
OE
t
CY7C09269V/79V/89V
CY7C09369V/79V/89V
t
SC
OLZ
n+1
t
OHZ
A
A
n+3
n+3
t
Q
OLZ
t
DC
n+2
t
t
HC
HC
t
t
OE
CKHZ
Page 8 of 19
Q
n+2
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