57C71C-55CMB STMicroelectronics, 57C71C-55CMB Datasheet

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57C71C-55CMB

Manufacturer Part Number
57C71C-55CMB
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of 57C71C-55CMB

Density
256Kb
Organization
32Kx8
Access Time (max)
55ns
Operating Current
60mA
Interface Type
Parallel
Operating Temperature Classification
Military
Operating Supply Voltage (typ)
5V
Operating Temp Range
-55C to 125C
Pin Count
32
Mounting
Surface Mount
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Lead Free Status / RoHS Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
57C71C-55CMB
Manufacturer:
WSI
Quantity:
155
BLOCK DIAGRAM
The WS57C71C is a High Performance 256K UV Erasable Electrically Re-Programmable Read Only Memory
(RPROM). It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate
EPROM cell.
The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8
device.
This RPROM is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used
directly with today's fast microprocessors and DSP processors without introducing any wait states. All inputs and
outputs are TTL compatible. The WS57C71C is a low power device even when operated at its fastest speed. The
DIP version is packaged in a 300 mil wide DIP package saving board space for the user.
PRODUCT SELECTION GUIDE
— 35 ns
Ultra-Fast Access Time
Fast Programming
Low Power Consumption
Address Access Time (Max)
CS to Output Valid Time (Max)
CS1/ V
CS2
A6 - A14
ROW
ADDRESSES
A0 - A5
COLUMN
ADDRESSES
CS3
PARAMETER
Return to Main Menu
PP
9
9
HIGH SPEED 32K x 8 CMOS PROM/RPROM
DECODER
ROW
EPROM ARRAY
262,144 BITS
AMPLIFIERS
DECODER
COLUMN
OUTPUTS
SENSE
8
GENERAL DESCRIPTION
WS57C71C-35
KEY FEATURES
35 ns
15 ns
PIN CONFIGURATION
NC
O
A
A
A
A
A
A
A
6
5
4
3
2
1
0
0
WS57C71C-45
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
O
4 3 2
1
Chip Carrier
O
45 ns
20 ns
Immune to Latch-UP
— Up to 200 mA
Available in 300 Mil DIP and PLDCC
ESD Protection Exceeds 2000V
2
NC O
1
32 31 30
3
O
4
O
29
28
27
26
25
24
23
22
21
5
TOP VIEW
WS57C71C-55
A
A
A
NC
CS3
CS2
CS1/V PP
O
O
12
13
14
7
6
55 ns
20 ns
GND
O
O
O
A
A
A
A
A
A
A
A
A
A
9
8
7
6
5
4
3
2
1
0
0
1
2
WS57C71C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CERDIP
WS57C71C-70
70 ns
30 ns
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
A 10
A 11
A 12
A 13
A 14
CS3
CS2
CS1/V PP
O
O
O
O
O
CC
7
6
5
4
3
2-55

Related parts for 57C71C-55CMB

57C71C-55CMB Summary of contents

Page 1

... It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate EPROM cell. The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8 device. This RPROM is capable of operating at speeds as fast address access time, which enables used directly with today's fast microprocessors and DSP processors without introducing any wait states ...

Page 2

... WS57C71C ABSOLUTE MAXIMUM RATINGS* Storage Temperature............................–65° 150°C Voltage on any Pin with Respect to Ground ....................................–0.6V to +7V V with Respect to Ground...................–0. 13V PP ESD Protection .................................................. * NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of ...

Page 3

... Address to Output Hold * Sampled, Not 100% Tested. AC READ TIMING DIAGRAM ADDRESSES CSX, CS2 OUTPUTS Over Operating Range. (See Above) 57C71C-35 57C71C-45 SYMBOL MIN MAX MIN t 35 ACC VALID t ACC t CS WS57C71C 57C71C-55 57C71C-70 MAX MIN MAX MIN MAX VALID t DF UNITS ns 2-57 ...

Page 4

... WS57C71C CAPACITANCE ( 25° MHz A SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT C V Capacitance VPP PP NOTES: 4. This parameter is only sampled and is not 100% tested. 5.Typical values are for T = 25°C and nominal supply voltages. A TEST LOAD (High Impedance Test Systems ...

Page 5

... NORMALIZED SUPPLY CURRENT 1.2 1.1 1.0 0.9 0.8 -55 -35 -15 85 105 125 WS57C71C vs. OUTPUT LOADING 200 400 600 800 1000 CAPACITANCE ( pF ) vs. AMBIENT TEMPERATURE 105 125 AMBIENT TEMPERATURE (°C) 2-59 ...

Page 6

... WS57C71C PROGRAMMING INFORMATION DC CHARACTERISTICS SYMBOLS Input Leakage Current Supply Current During Programming Pulse I V Supply Current CC CC Output Low Voltage During Verify mA) OL Output High Voltage During Verify –4 mA) OH NOTE must not be greater than 13 volts including overshoot CHARACTERISTICS SYMBOLS t Address Setup Time ...

Page 7

... ORDERING INFORMATION SPEED PART NUMBER (ns) WS57C71C-35J 35 WS57C71C-35L 35 WS57C71C-35T 35 WS57C71C-45CI 45 WS57C71C-45D 45 WS57C71C-45J 45 WS57C71C-45T 45 WS57C71C-45TMB 45 WS57C71C-55CMB 55 WS57C71C-55D 55 WS57C71C-55DMB 55 WS57C71C-55J 55 WS57C71C-55JI 55 WS57C71C-55L 55 WS57C71C-55T 55 WS57C71C-55TI 55 WS57C71C-55TMB 55 WS57C71C-70L 70 WS57C71C-70T 70 WS57C71C-70TMB 70 NOTE: 8. The actual part marking will not include the initials "WS." PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS The WS57C71C is programmed using Algorithm D shown on page 5-9. ...

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