STK11C88-3NF35I Cypress Semiconductor Corp, STK11C88-3NF35I Datasheet - Page 7

• Manufacturer Part Number: STK11C88-3NF35I
• Manufacturer: Cypress Semiconductor Corp

Specifications of STK11C88-3NF35I

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The STK11C88-3 is a versatile 3.3V V
chip that provides several modes of operation. The
STK11C88-3 can operate as a standard 32K x 8
SRAM
shadow to which the
ied or from which the
volatile mode.
NOISE CONSIDERATIONS
Note that the STK11C88-3 is a high-speed memory
and so must have a high frequency bypass capaci-
tor of approximately 0.1μF connected between V
and V
possible. As with all high-speed
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK11C88-3 performs a
E and G are low and W is high. The address speci-
fied on pins A
data bytes will be accessed. When the
ated by an address transition, the outputs will be
valid after a delay of t
READ
at t
The data outputs will repeatedly respond to address
changes within the t
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
SRAM WRITE
A
low. The address inputs must be stable prior to
entering the
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
March 2006
WRITE
ELQV
. It has a 32K x 8 Nonvolatile Elements
SS
is initiated by E or G, the outputs will be valid
WRITE
or at t
, using leads and traces that are as short as
cycle is performed whenever E and W are
WRITE
GLQV
WRITE
cycle to avoid data bus contention on
0-14
, whichever is later (
WRITE
determines which of the 32,768
.
AVQV
cycle and must remain stable
SRAM
SRAM
AVQV
access time without the need
or t
DVEH
information can be cop-
(
can be updated in non-
READ
WLQZ
READ
before the end of an
DVWH
CMOS
after W goes low.
cycle #1). If the
cycle whenever
READ
DEVICE OPERATION
before the end
0-7
READ
ICs, normal
will be writ-
CC
cycle #2).
memory
is initi-
CC
7
SOFTWARE NONVOLATILE STORE
The STK11C88-3 software
by executing sequential
cific address locations. During the
erase of the previous nonvolatile data is first per-
formed, followed by a program of the nonvolatile
elements. The program operation copies the
data into nonvolatile memory. Once a
is initiated, further input and output are disabled until
the cycle is completed.
Because a sequence of reads from specific
addresses is used for
tant that no other
vene in the sequence, or the sequence will be
aborted and no
To initiate the software
READ
The software sequence is clocked with E controlled
READ
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
and not
although it is not necessary that G be low for the
sequence to be valid. After the t
been fulfilled, the
READ
SOFTWARE NONVOLATILE RECALL
A software
of
ware
the following sequence of
performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
READ
Document Control # ML0013 rev 0.2
s.
STORE
sequence must be performed:
and
operations in a manner similar to the soft-
WRITE
WRITE
RECALL
initiation. To initiate the
STORE
STORE
cycles be used in the sequence,
operation.
SRAM
READ
cycle is initiated with a sequence
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
cycle will commence and the
STORE
or
STORE
READ
will again be activated for
or
RECALL
READ
STORE
WRITE
initiation, it is impor-
cycles from six spe-
cycle, the following
STORE
operations must be
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
STK11C88-3
will take place.
cycle is initiated
STORE
accesses inter-
cycle time has
RECALL
STORE
READ
cycle an
cycles
SRAM
cycle,
cycle