STK15C68-W45 Cypress Semiconductor Corp, STK15C68-W45 Datasheet - Page 8

• Manufacturer Part Number: STK15C68-W45
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK15C68-W45

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 65mA
• Lead Free Status / RoHS Status: Not Compliant

March 2006
STK15C68
Internally,
the
tile information is transferred into the
After the t
be ready for
RECALL
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
AutoStore™ OPERATION
The STK15C68 uses the intrinsic system capaci-
tance to perform an automatic store on power
down. As long as the system power supply takes at
least t
STK15C68 will safely and automatically store the
SRAM
down.
In order to prevent unneeded
automatic
one
most recent
initiated
whether a
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
CC
SRAM
WRITE
< V
STORE
100
80
60
40
20
data in Nonvolatile Elements on power
0
STORE
operation in no way alters the data in the
RESET
RECALL
data is cleared, and second, the nonvola-
WRITE
RECALL
STORE
to decay from V
SWITCH
Figure 2: I
operation has taken place since the
), an internal
STORE
READ
cycle time the
cycles are performed regardless of
, a
CC
50
operation has taken place.
will be ignored unless at least
is a two-step procedure. First,
once again exceeds the sense
RECALL
and
or
CC
Cycle Time (ns)
100
RESTORE
RECALL
(max) Reads
WRITE
RECALL
SWITCH
cycle will automatically
SRAM
150
STORE
to complete.
down to 3.6V, the
TTL
CMOS
cycle. Software-
operations. The
request will be
will once again
200
SRAM
operations,
cells.
8
If the STK15C68 is in a
power-up
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
HARDWARE PROTECT
The STK15C68 offers hardware protection against
inadvertent
during low-voltage conditions. When V
software
inhibited.
LOW AVERAGE ACTIVE POWER
The STK15C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
perature range, V
enable). Figure 3 shows the same relationship for
WRITE
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK15C68 depends on the following items:
1)
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
temperature; 6) the V
CC
CMOS
or between E and system V
Document Control # ML0009 rev 0.2
CMOS
100
cycles. If the chip enable duty cycle is less
80
60
40
20
0
STORE
vs.
RECALL
and
STORE
Figure 3: I
TTL
READ
TTL
operations and
50
CC
, the
input levels; 2) the duty cycle of
= 5.5V, 100% duty cycle on chip
operation and
s to
input levels (commercial tem-
CC
Cycle Time (ns)
CC
SRAM
level; and 7) I/O loading.
100
WRITE
WRITE
(max) Writes
data will be corrupted.
150
CC
s; 5) the operating
state at the end of
CC
SRAM WRITE
TTL
.
CMOS
and
SRAM WRITE
200
CC
READ
< V
SWITCH
s are
cycle
s
,