M368L3223FUN-CCC Samsung Semiconductor, M368L3223FUN-CCC Datasheet - Page 15

• Manufacturer Part Number: M368L3223FUN-CCC
• Manufacturer: Samsung Semiconductor

Specifications of M368L3223FUN-CCC

• Lead Free Status / RoHS Status: Compliant

128MB, 265MB, 512MB Unbuffered DIMM
AC Timing Parameters and Specifications
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Internal write to read command delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
Write preamble setup time
Write preamble
Write postamble
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time
Address and Control Input hold time
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS, slew rate 0.5V/ns
DQ & DM hold time to DQS, slew rate 0.5V/ns
DQ & DM input pulse width
Control & Address input pulse width for each input
Refresh interval time
Output DQS valid window
Clock half period
Parameter
CL=3.0
CL=2.5
tWPRES
tDQSCK
Symbol
tDQSQ
tWPRE
tWPST
tRPRE
tDQSS
tDQSH
tRPST
tDQSL
tDIPW
tWTR
tMRD
tREFI
tRCD
tRRD
tDSH
tRFC
tRAS
tDSS
tIPW
tWR
tDH
tQH
tRC
tRP
tCK
tCH
tAC
tHZ
tDS
tHP
tCL
tLZ
tIS
tIH
tAC min
tCH/tCL
CC(DDR400@CL=3)
-tQHS
-0.55
-0.65
0.45
0.45
0.72
0.25
0.35
0.35
1.75
Min
tHP
min
0.9
0.4
0.4
0.2
0.2
0.6
0.6
0.4
0.4
2.2
55
70
40
15
15
10
15
2
5
6
0
2
-
-
tAC max
tAC max
+0.55
+0.65
Max
0.55
0.55
1.28
70K
0.4
1.1
0.6
0.6
7.8
10
12
-
-
tAC min
tCH/tCL
C4(DDR400@CL=3)
-tQHS
-0.55
-0.65
0.45
0.45
0.72
0.25
0.35
0.35
1.75
Min
tHP
min
0.9
0.4
0.4
0.2
0.2
0.6
0.6
0.4
0.4
2.2
70
40
60
18
18
10
15
2
5
6
0
2
-
-
Rev. 1.0 October. 2004
tAC max
tAC max
+0.55
+0.65
Max
0.55
0.55
1.28
70K
1.1
0.6
0.6
0.4
7.8
10
12
-
-
DDR SDRAM
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
h,7~10
h,7~10
11, 12
Note
16
13
12
i, j
i, j
5
4
3
3
9
9
6