HB28D032MM2 Renesas Electronics America, HB28D032MM2 Datasheet - Page 53

• Manufacturer Part Number: HB28D032MM2
• Manufacturer: Renesas Electronics America

Specifications of HB28D032MM2

• Lead Free Status / RoHS Status: Compliant

• Stream read
The data transfer starts N
identical to that of a read block command (refer to Figure “Data Read Timing”). As the data transfer is not
block-oriented, the data stream does not include the CRC checksum. Consequently the host can not check
for data validity. The data stream is terminated by a stop command. The corresponding bus transaction is
identical to the stop command for the multiple read block (refer to Figure “Timing of Stop Command”).
• Single or multiple block write
The host selects one card for data write operation by CMD7. The host sets the valid block length for
block-oriented data transfer by CMD16 (The write-block-length of the Hitachi MultiMediaCard is
permanently assigned to the value 512 bytes). The host transfers the data with CMD24. The address of the
data block is determined by the argument of this command. This command is responded by the card on the
CMD line as usual. The data transfer from the host starts N
received. The write data have CRC check bits to allow the card to check the transferred data for
transmission errors. The card sends the CRC check information as a CRC status to the host (on the data
line). The CRC status contains the information if the write data transfer was non-erroneous (the CRC
check did not fail) or not. In the case of transmission error the card sends a negative CRC status (“101”
bin) which forces the host to retransmit command and the data. In the case of non-erroneous transmission
the card sends a positive CRC status (“010” bin) and starts the data programming procedure.
If the card does not have any more free data receive buffer, the card indicates it by pulling down the data
line to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the
defined data transfer block length becomes free. This signaling does not give any information about the
data write status. This information has to be polled by the status polling command (SEND_STATUS).
CMD
CMD
DAT
DAT
L ... pull down to LOW bit
S T
Z Z Z
Host command
content
Host active
content
Host active
Write data
* * * *
AC
clock cycles after the end bit of the host command. The bus transaction is
Z
CRC E
CRC E
Z
Z
Timing of The Block Write Command
Z Z Z Z Z Z
N
Z Z S
CR
S T
CRC status
status
Card response
Card active
content
Card active
* * * *
HB28H016/D032/B064/B128MM2
E S
WR
Z Z Z Z
clock cycles after the card response was
Card busy
busy = 'L'
CRC E
N
Z P
Rev.5.0, Jan. 2003, page 51 of 88
E
WR
Z
S
Host active
Write data
content