CY7C265-50DMB Cypress Semiconductor Corp, CY7C265-50DMB Datasheet

CY7C265-50DMB

Manufacturer Part Number

CY7C265-50DMB

Description

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.CY7C265-50DMB.pdf (11 pages)

Specifications of CY7C265-50DMB

Density

64Kb

Access Time (max)

25ns

Supply Current

120mA

Pin Count

Mounting

Through Hole

Operating Temperature Classification

Military

Lead Free Status / RoHS Status

Not Compliant

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Manufacturer

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Price

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BOSTOCK HK LIMITED

Part Number:

CY7C265-50DMB

Manufacturer:

Quantity:

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Features

Functional Description

The CY7C265 is a 8192 x 8 registered PROM. It is organized

as 8,192 words by 8 bits wide, and has a pipeline output

initialize byte that may be loaded into the pipeline register with

the initialize signal. The programmable initialize byte is the

8,193rd byte in the PROM and its value is programmed at the

time of use.

Packaged in 28 pins, the PROM has 13 address signals (A

through A

or initialize), and CLOCK.

CLOCK functions as a pipeline clock, loading the contents of

the addressed memory location into the pipeline register on

each rising edge. The data will appear on the outputs if they

are enabled. One pin on the CY7C265 is programmed to

perform either the enable or the initialize function.

Cypress Semiconductor Corporation

Document #: 38-04012 Rev. *A

• CMOS for optimum speed/power

• High speed (Commercial)

• Low power

• On-chip edge-triggered registers

• EPROM technology

• 5V ±10% V

• Capable of withstanding >2001V static discharge

• Slim 28-pin, 300-mil plastic or hermetic DIP

— 15 ns address set-up

— 12 ns clock to output

— 660 mW (Commercial)

— Ideal for pipelined microprogrammed systems

— 100% programmable

— Reprogrammable (CY7C265W)

), 8 data out signals (O

, commercial and military

through O

•

3901 North First Street

), E/I (enable

If the asynchronous enable (E) is being used, the outputs may

be disabled at any time by switching the enable to a logic

HIGH, and may be returned to the active state by switching the

enable to a logic LOW.

If the synchronous enable (E

go to the OFF or high-impedance state upon the next positive

clock edge after the synchronous enable input is switched to

a HIGH level. If the synchronous enable pin is switched to a

logic LOW, the subsequent positive clock edge will return the

output to the active state. Following a positive clock edge, the

address and synchronous enable inputs are free to change

since no change in the output will occur until the next

LOW-to-HIGH transition of the clock. This unique feature al-

lows the CY7C265 decoders and sense amplifiers to access

the next location while previously addressed data remains sta-

ble on the outputs.

If the E/I pin is used for INIT (asynchronous), then the outputs

are permanently enabled. The initialize function is useful

during power-up and time-out sequences, and can facilitate

implementation of other sophisticated functions such as a

built-in “jump start” address. When activated, the initialize

control input causes the contents of a user programmed

8193rd 8-bit word to be loaded into the on-chip register. Each

bit is programmable and the initialize function can be used to

load any desired combination of 1’s and 0’s into the register.

In the unprogrammed state, activating INIT will generate a

word are programmed to be a 1, activating INIT performs a

Applying a LOW to the INIT input causes an immediate load

of the programmed initialize word into the pipeline register and

onto the outputs. The INIT LOW disables clock and must

return HIGH to enable clock independent of all other inputs,

including the clock.

•

8K x 8 Registered PROM

San Jose

•

CA 95134

) is being used, the outputs will

Revised October 9, 2002

•

CY7C265

408-943-2600

Related parts for CY7C265-50DMB

CY7C265-50DMB Summary of contents

Page 1

... Capable of withstanding >2001V static discharge • Slim 28-pin, 300-mil plastic or hermetic DIP Functional Description The CY7C265 is a 8192 x 8 registered PROM organized as 8,192 words by 8 bits wide, and has a pipeline output register. In addition, the device features a programmable initialize byte that may be loaded into the pipeline register with the initialize signal ...

Page 2

... Pin Configurations DIP/Flatpack Top View 7C265 GND CLK GND LCC/PLCC (Opaque Only) O Top View GND 7 CLK GND 7C265-40 7C265- 100 120 Ambient Temperature +70 C [1] – +125 C is the “instant on” case temperature. CY7C265 E GND GND E GND 21 20 GND Unit 10% 5V 10% Page ...

Page 3

... CC Output Disabled V = Max GND CC OUT V = Max Com’l CC OUT Mil 3.0 Test Conditions T = 25° MHz 5.0V CC CY7C265 7C265-40 7C265-50 Max. Min. Max. Min. Max. Unit 2.4 2.4 0.4 0.4 0.4 0.4 0.4 2.0 2.0 0.8 0.8 0.8 +10 –10 +10 –10 +10 +40 – ...

Page 4

... MIL 333 5 pF (403 MIL) INCLUDING JIG AND SCOPE (b) High Z Load 250 MIL R1 250 167 INCLUDING JIG AND SCOPE (d) High Z Load 2.0V [2, 4] 7C265-15 7C265-25 Min. Max. Min CY7C265 3.0V 90% 90% 10% GND 5 ns 7C265-40 7C265-50 Max. Min. Max. Min. Max ...

Page 5

... Once the supervoltages have been established and the Contents correct logic states exist on the other device pins, Data programming may begin. Programming is accomplished by . pulling PGM from HIGH to LOW and then back to HIGH with . a pulse width equal to 10 ms. Data INIT Byte Control Byte CY7C265 DOE t HZE Page ...

Page 6

... PGM CLK VFY Figure 1. Programming Pinout programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. CY7C265 Pin Function – – – – – – –A ...

Page 7

... 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) NORMALIZED SUPPLY CURRENT vs. CLOCK PERIOD 1.05 1. 5. 0.90 0.85 0.80 0.75 0. CLOCK PERIOD (ns) CY7C265 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 125 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING =4. 200 ...

Page 8

... Ordering Information Speed I CC (ns) (mA) Ordering Code 15 120 CY7C265-15JC CY7C265-15WC 25 120 CY7C265-25PC CY7C265-25WC 40 100 CY7C265-40PC 50 120 CY7C265-50DMB MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Document #: 38-04012 Rev. *A Package Name J64 28-Lead Plastic Leaded Chip Carrier W22 28-Lead (300-Mil) Windowed CerDIP P21 ...

Page 9

... Package Diagrams Document #: 38-04012 Rev. *A 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D-15 Config. A 28-Lead Plastic Leaded Chip Carrier J64 CY7C265 51-80032-** 51-85001-*A Page ...

Page 10

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D-15 Config. A CY7C265 51-85014-*B 51-80087-** Page ...

Page 11

... Document History Page Document Title: CY7C265 Registered PROM Document Number: 38-04012 Issue REV. ECN NO. Date ** 114139 03/18/02 *A 118896 10/09/02 Document #: 38-04012 Rev. *A Orig. of Change DSG Change from Spec number: 38-00084 to 38-04012 GBI Update ordering information CY7C265 Description of Change Page ...

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