IS42S81600B-7TL-TR ISSI, Integrated Silicon Solution Inc, IS42S81600B-7TL-TR Datasheet - Page 2

• Manufacturer Part Number: IS42S81600B-7TL-TR
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S81600B-7TL-TR

• Organization: 16Mx8
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 120mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

rows by 1,024 columns by 8 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
and 3.3V V
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nized as 4,096 rows by 512 columns by 16 bits or 4,096
IS42S81600B, IS42S16800B
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONlY)
2
CKE
RAS
CAS
A10
CLK
BA0
BA1
A11
WE
CS
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ddq
memory systems containing 134,217,728
GENERATOR
COMMAND
DECODER
12
CLOCK
&
ADDRESS
LATCH
ROW
9
ADDRESS BUFFER
BURST COUNTER
ADDRESS LATCH
REGISTER
MODE
COLUMN
COLUMN
12
Integrated Silicon Solution, Inc. — www.issi.com —
12
CONTROLLER
COUNTER
REFRESH
REFRESH
CONTROLLER
REFRESH
ADDRESS
BUFFER
dd
SELF
ROW
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
BANK CONTROL LOGIC
12
4096
16
16
4096
4096
4096
DATA OUT
BUFFER
BUFFER
9
DATA IN
(x 16)
COLUMN DECODER
512
SENSE AMP I/O GATE
MEMORY CELL
BANK 0
16
16
ARRAY
2
DQML
DQMH
DQ 0-15
V
V
DD
ss
1-800-379-4774
/V
/V
ss
DDQ
Q
06/11/09
Rev. G