LRS1392A Sharp Electronics, LRS1392A Datasheet - Page 39

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LRS1392A

Manufacturer Part Number
LRS1392A
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LRS1392A

Lead Free Status / RoHS Status
Supplier Unconfirmed
sharp
17. Design Considerations
18. Related Document Information
Note:
1. International customers should contact their local SHARP or distribution sales offices.
1. Power Supply Decoupling
2. F-V
3. The Inhibition of Overwrite Operation
4. Power Supply
To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a 0.1µ F
ceramic capacitor connected between its F-V
Low inductance capacitors should be placed as close as possible to package leads.
Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board
designer pay attention to the F-V
V
Please do not execute reprograming “0” for the bit which has already been programed “0”. Overwrite operation may
generate unerasable bit.
In case of reprograming “0” to the data which has been programed “1”.
For example, changing data from “1011110110111101” to “1010110110111100”
requires “1110111111111110” programing.
Block erase, full chip erase, (page buffer) program and OTP program with an invalid F-V
Electrical Characteristics) produce spurious results and should not be attempted.
Device operations at invalid F-V
and should not be attempted.
CC
PP
power bus.
• Program “0” for the bit in which you want to change data from “1” to “0”.
• Program “1” for the bit which has already been programed “0”.
Trace on Printed Circuit Boards
Document No.
FUM00701
(1)
PP
CC
Power Supply trace. Use similar trace widths and layout considerations given to the F-
LH28F320BF, LH28F640BF, LH28F128BF Series Appendix
voltage (See Chapter 11. DC Electrical Characteristics) produce spurious results
CC
and GND and between its F-V
L R S 1 3 9 2 A
Document Name
PP
and GND.
PP
(See Chapter 11. DC
36

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