AT52BC6402AT-70CU Atmel, AT52BC6402AT-70CU Datasheet - Page 3

• Manufacturer Part Number: AT52BC6402AT-70CU
• Manufacturer: Atmel

Specifications of AT52BC6402AT-70CU

• Operating Supply Voltage (max): 3.1V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

64-Mbit Flash
Description
Device Operation
3441B–STKD–11/04
The 64-Mbit Flash memory is divided into multiple sectors and planes for erase opera-
tions. The devices can be read or reprogrammed off a single 2.7V power supply, making
them ideally suited for in-system programming.
The 64-Mbit device is divided into four memory planes. A read operation can occur in
any of the three planes which is not being programmed or erased. This concurrent oper-
ation allows improved system performance by not requiring the system to wait for a
program or erase operation to complete before a read is performed. To further increase
the flexibility of the device, it contains an Erase Suspend and Program Suspend feature.
This feature will put the erase or program on hold for any amount of time and let the user
read data from or program data to any of the remaining sectors. There is no reason to
suspend the erase or program operation if the data to be read is in another memory
plane. The end of program or erase is detected by Data Polling or toggle bit.
The VPP pin provides data protection and faster programming and erase times. When
the V
at 1.65V or above, normal program and erase operations can be performed. With V
12.0V, the program and erase operations are accelerated.
With V
requirement of entering the three-byte program sequence is offered to further improve
programming time. After entering the six-byte code, only single pulses on the write con-
trol lines are required for writing into the device. This mode (Single Pulse Word
Program) is exited by powering down the device, by taking the RESET pin to GND or by
a high-to-low transition on the V
pend/Resume and Read Reset commands will not work while in this mode; if entered
they will result in data being programmed into the device. It is not recommended that the
six-byte code reside in the software of the final product but only exist in external pro-
gramming code.
COMMAND SEQUENCES: The device powers on in the read mode. Command
sequences are used to place the device in other operating modes such as program and
erase. After the completion of a program or an erase cycle, the device enters the read
mode. The command sequences are written by applying a low pulse on the WE input
with CE low and OE high or by applying a low-going pulse on the CE input with WE low
and OE high. The address is latched on the falling edge of the WE or CE pulse which-
ever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,
whichever occurs first. The addresses used in the command sequences are not affected
by entering the command sequences.
ASYNCHRONOUS READ: The 64-Mbit Flash is accessed like an EPROM. When CE
and OE are low and WE is high, the data stored at the memory location determined by
the address pins are asserted on the outputs. The outputs are put in the high impedance
state whenever CE or OE is high. This dual-line control gives designers flexibility in pre-
venting bus contention.
RESET: A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET pin halts the present device operation and puts the outputs of the device
in a high-impedance state. When a high level is reasserted on the RESET pin, the
device returns to read or standby mode, depending upon the state of the control pins.
PP
PP
input is below 0.8V, the program and erase functions are inhibited. When V
at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove the
PP
input. Erase, Erase Suspend/Resume, Program Sus-
AT52BC6402A(T)
PP
PP
at
is
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