S71VS128RC0AHK4L0 Spansion Inc., S71VS128RC0AHK4L0 Datasheet - Page 7

• Manufacturer Part Number: S71VS128RC0AHK4L0
• Manufacturer: Spansion Inc.

Specifications of S71VS128RC0AHK4L0

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.
April 9, 2010 S71VS_XS-R_00_08
Input/Output Descriptions
Table 2.1
AMAX – A16
A/DQ15-A/DQ0
OE#
WE#
V
V
NC
F-RDY/R-WAIT
CLK
AVD#
F-RST#
F-V
R-CE#
F-CE#
R-CRE
V
V
R-UB#
R-LB#
RFU
SS
SSQ
CC
CCQ
PP
Symbol
identifies the input and output package connections provided on the device.
Address inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
Input/Output Ground
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default “Active HIGH” configuration)
V
V
Note: The default polarity for the pSRAM WAIT signal is opposite the default polarity of the
Flash RDY signal.
pSRAM WAIT (using default “Active HIGH” configuration)
V
V
To match polarities, change bit 10 of the pSRAM Bus Configuration Register to 0 (Active
LOW WAIT). Alternately, change bit 10 of the Flash Configuration Register to 0 (Active LOW
RDY)
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at V
Address Valid input. Indicates to device that the valid address is present on the address
inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched.
High = device ignores address inputs
Accelerated input. At V
bypass mode. At V
conditions.
Chip-enable input for pSRAM.
Flash and pSRAM 1.8 Volt-only single power supply.
Flash and pSRAM Input/Output Power Supply
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
No Connect; not connected internally
Hardware reset input. Low = device resets and returns to reading array data
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
Control Register Enable (pSRAM).
Reserved For Future Use
OL
OH
OL
OH
= data invalid
= data valid
= data valid
= data invalid
S71VS/XS-R Memory Subsystem Solutions
D a t a
IL
, disables all program and erase functions. Should be at V
HH
S h e e t
, accelerates programming; automatically places device in unlock
Table 2.1 Input/Output Descriptions
Description
IL
or V
IH
while in asynchronous mode
IH
for all other
Flash
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RAM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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