LTC4251-1CS6#PBF Linear Technology, LTC4251-1CS6#PBF Datasheet - Page 14

• Manufacturer Part Number: LTC4251-1CS6#PBF
• Manufacturer: Linear Technology

Specifications of LTC4251-1CS6#PBF

• Family Name: LTC4251-1
• Package Type: TSOT-23
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Height (mm): 0.9mm
• Product Length (mm): 2.9mm
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / RoHS Status: Compliant

LTC4251/LTC4251-1/
LTC4251-2
APPLICATIO S I FOR ATIO
C
based on this criterion. The IRF530S can handle 100V and
3A for 10ms, and is safe to use in this application.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 2, which was designed for 50W:
Calculate maximum load current: 50W/36V = 1.4A; allow-
ing 83% converter efficiency, I
Calculate R
Calculate C
correction factor).
Calculate TIMER period: from Equation (2) the short-
circuit time-out period is t = 2.6ms.
Calculate maximum short-circuit current: from Equation
(5) maximum short-circuit current could be as high as
120mV/20mΩ = 6A.
Consult MOSFET SOA curves: the IRF530S can handle 6A
at 72V for 5ms, so it is safe to use in this application.
FREQUENCY COMPENSATION
The LTC4251/LTC4251-1/LTC4251-2 typical frequency
compensation network for the analog current limit loop is
a series R
depicts the relationship between the compensation ca-
pacitor C
used to select a starting value for C
MOSFET’s C
shown for several popular MOSFETs. Differences in the
optimized value of C
Nevertheless, compensation values should be verified by
board level short-circuit testing.
As seen in Figure 4 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
cally owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
14
T
= 330nF in Equation (2). The MOSFET must be selected
C
C
T
and the MOSFET’s C
S
: from Equation (7) C
ISS
: from Equation (3) R
(10Ω) and C
specification. Optimized values for C
U
C
versus the starting value are small.
U
C
connected to V
IN (MAX)
ISS
T
= 150nF (including 1.5X
S
. The line in Figure 5 is
W
= 20mΩ.
C
= 1.7A.
based upon the
EE
U
. Figure 5
C
are
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the V
SENSE pins are strongly recommended. The drawing in
Figure 6 illustrates the correct way of making connections
between the LTC4251/LTC4251-1/LTC4251-2 and the
sense resistor. PCB layout should be balanced and sym-
metrical to minimize wiring errors. In addition, the PCB
layout for the sense resistor should include good thermal
management techniques for optimal sense resistor power
dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 7 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV
Figure 6. Making PCB Connections to the Sense Resistor
TRACK WIDTH W:
ON 1 OZ COPPER
0.03" PER AMP
Figure 5. Recommended Compensation
Capacitor C
CURRENT FLOW
FROM LOAD
60
50
40
30
20
10
0
0
IRF530
W
IRF740
IRF540
C
2000
vs MOSFET C
IRF3710
SENSE
MOSFET C
SENSE RESISTOR
TO
4000
ISS
(pF)
V
TO
EE
MTY100N10E
6000
ISS
TO –48V BACKPLANE
425112 F05
CURRENT FLOW
8000
425112 F06
EE
425112fa
and