ADL5202XCPZ-R7 Analog Devices Inc, ADL5202XCPZ-R7 Datasheet - Page 9

• Manufacturer Part Number: ADL5202XCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of ADL5202XCPZ-R7

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Preliminary Technical Data
DIGITAL INTERFACE OVERVIEW
The ADL5202 DVGA has three digital control interface options:
The digital control interface selection is made via 2 digital pins,
MODE1 and MODE0, as shown in Table 5. There are two
common digital control pins, PM and PWUP. PM selects
between two power modes. PWUP is a power up pin. The gain
code used is 6 bit binary.
Physical pins are shared between 3 interfaces resulting in as
many as 3 different functions per digital pin (see Table 4)
Table 5. Digital control interface selection truth table
MODE1
0
0
1
1
Parallel Digital Interface
The parallel digital interface uses 6 gain control bits and a latch
pin per amplifier. The latch pin controls whether the input data
latch is transparent or latched. In transparent mode, gain
changes as input gain control bits change. In latched mode,
gain is determined by the latched gain setting and does not
change with changing input gain control bits.
Serial Peripheral Interface (SPI)
The SPI uses 3 pins (SDIO, SCLK, and /CSA or /CSB). The SPI
data register consists of 2 bytes: 6 gain control bits, 2
attenuation step size address bits, 1 read/write bit, and 7 do not
care bits.
The SPI uses a bidirectional pin, SDIO, for writing to the SPI
register and for reading from the SPI register. In order to write to
the SPI register, CSA or CSB needs to be pulled low and 16 clock
pulses must be applied. Individual channel SPI registers can be
selected by pulling low CSA or CSB. By simultaneously pulling
low the CSA and CSB pins, the same data can be written to both
SPI registers.
In order to read the SPI register value, the R/W bit needs to be
set high, CSA or CSB needs to be pulled low, and the part
clocked. Once the register has been read out the R/W bit needs
to be set low and SPI put in write mode. Note that there is only
one SDIO pin. Read back from the registers should be done
individually.
•
•
•
Parallel Control Interface
Serial Peripheral Interface
Gain Step Up/Down Interface
MODE0
0
1
0
1
Interface
Parallel
Serial (SPI)
Up/Down
Up/Down
Rev. PrE | Page 9 of 13
SPI fast attack mode is controlled by FA_A or FA_B. A logic
high on the FA pin results in an attenuation selected by FA1 and
FA0 bits in the SPI register.
Table 6. SPI 2-bit attenuation step size truth table
FA1
0
0
1
1
UP/DOWN Interface
The UP/DOWN interface uses two digital pins to control the
gain. Gain is increased by a clock pulse on UPDN_CLK (rising
and falling edges) when UPDN_DAT is high. Gain is decreased
by a clock pulse on UPDN_CLK when UPDN_DAT is low.
Reset is detected by a rising edge latching data having one
polarity with the falling edge latching the opposite polarity.
Reset results in minimum gain code 111111
The step size is selectable by pins GS1 and GS0. The default
step size is 0.5dB. The gain code count will rail at the top and
bottom of the control range.
Table 7. Step size control truth table
GS1
0
0
1
1
UPDN_DAT
UPDN_CLK
UP
Figure 4. 16- bit SPI Register
Figure 3. UP/DOWN Timing
FA0
0
1
0
1
GS0
0
1
0
1
DN
Step Size (dB)
2
4
8
16
Step Size (dB)
0.5
1
2
4
bin
.
RESET
ADL5202