AD9101SE Analog Devices Inc, AD9101SE Datasheet - Page 3

• Manufacturer Part Number: AD9101SE
• Manufacturer: Analog Devices Inc

Specifications of AD9101SE

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Lead Free Status / RoHS Status: Not Compliant

NOTES
1
2
3
4
5
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (+V
Supply Voltage (–V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V
CLOCK/CLOCK Input . . . . . . . . . . . . . . . . . –5 V to +0.5 V
Continuous Output Current
Storage Temperature . . . . . . . . . . . . . . . . . . –65 C to +150 C
Operating Temperature Range
Junction Temperature (Ceramic)
Junction Temperature (Plastic)
Soldering Temperature (1 minute)
NOTES
1
2
3
4
EXPLANATION OF TEST LEVELS
Test Level
I
II – 100% production tested at +25 C, and sample tested at
III – Periodically sample tested.
IV – Parameter is guaranteed by design and characterization
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25 C. 100%
Model
AD9101AR
AD9101AE
AD9101SE
REV. 0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9101 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
If the analog input exceeds 300 mV, the clock levels should be shifted as shown in the Theory of Operation section entitled “Driving the Encode Clock.”
Time to recover within rated error band from 160% overdrive.
Sampling bandwidth is defined as the –3 dB frequency response of the input sampler to the hold capacitor when operating in the sampling mode. It is greater than
Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t
Total energy of worst case track-to-hold or hold-to-track glitch.
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
Typical thermal impedances (no air flow, soldered to PC board) are as follows:
Ceramic LCC:
For surface mount devices, mounted by vapor phase soldering. Prior to vapor phase
soldering, plastic units should receive a minimum eight hour bakeout at 110 C to
drive off any moisture absorbed in plastic during shipping or storage. Through-hole
devices can be soldered at +300 C for 10 seconds.
Output is short circuit protected to ground. Continuous short circuit may affect
device reliability.
tracking bandwidth because it does not include the bandwidth of the output amplifier.
(150 mV/s
JC
AE, AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 C to +85 C
SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to +125 C
= 7.3 C/W.
– 100% production tested.
specified temperatures.
testing.
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
20 ns). This value must be combined with the track mode noise to obtain total noise.
JA
Temperature
Range
–40 C to +85 C
–40 C to +85 C
–55 C to +125 C
= 48 C/W;
ORDERING INFORMATION
S
S
) . . . . . . . . . . . . . . . . . . . . –6 V to +0.5 V
) . . . . . . . . . . . . . . . . . . . . –0.5 V to +6 V
JC
4
= 9.9 C/W; Plastic SOIC:
. . . . . . . . . . . . . . . . . . . . 70 mA
2
2
. . . . . . . . . . . . . . . . +150 C
3
. . . . . . . . . . . . . . . +175 C
. . . . . . . . . . . . . . +220 C
1
Package
Description
Plastic SOIC
LCC
LCC
JA
Package
Option
E-20A
E-20A
R-20
= 54 C/W;
–3–
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
*See “Matching the AD9101 to A/D Encoders.” Both pins should be either
grounded or connected to voltage source for offset.
GND
GND
RTN
RTN
CLK
C
+V
+V
+V
+V
B+
S
S
S
S
Description
RTN
RTN
C
+V
+V
GND
GND
+V
+V
CLK
CLK
–V
–V
N/C
V
GND
–V
–V
C
V
10
1
2
3
4
5
9
6
7
8
IN
OUT
B+
B–
20-Pin SOIC
S
S
S
S
S
S
S
S
(Not to Scale)
H
AD9101
TOP VIEW
) is 20 ns, the accumulated noise is typically 3 V
PIN CONFIGURATIONS
20
19
18
17
16
15
14
13
12
11
Connection
Gain Set Resistor Return*
Gain Set Resistor Return*
Bootstrap Capacitor (Positive Bias)
+5 V Power Supply (Analog)
+5 V Power Supply (Analog)
Hold Capacitor Ground
Hold Capacitor Ground
+5 V Power Supply (Digital)
+5 V Power Supply (Digital)
True ECL T/H Clock
Complement ECL T/H Clock
–5.2 V Power Supply (Digital)
–5.2 V Power Supply (Digital)
No Connection
Analog Signal Input
Ground (Signal Return)
–5.2 V Power Supply (Analog)
–5.2 V Power Supply (Analog)
Bootstrap Capacitor (Negative Bias)
Analog Signal Output
V
C
–V
–V
GND
V
NC
–V
–V
CLK
OUT
B–
IN
S
S
S
S
GND
WARNING!
–V
–V
20-Contact Ceramic LCC
V
NC
IN
S
S
18
17
16
15
14
19 20
13
BOTTOM VIEW
12
ESD SENSITIVE DEVICE
11
1
10
2
AD9101
3
9
5
4
6
7
8
+V
+V
+V
GND
GND
S
S
S