LF198WG/883 National Semiconductor, LF198WG/883 Datasheet - Page 6

• Manufacturer Part Number: LF198WG/883
• Manufacturer: National Semiconductor

Specifications of LF198WG/883

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Pin Count: 14
• Lead Free Status / RoHS Status: Not Compliant

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V
(2nd Stg)
T
V
I
IB
OS
AQ
OS
Electrical Characteristics
Symbol
Symbol
Symbol
The following specifications apply unless otherwise specified. V
erence Pin = 0V, Logic Pin = 4V
AC Parameters
The following specifcations apply unless otherwise specified. V
ence Pin = 0V, Logic Pin = 4V
DC Parameters: Drift Values
The following conditions apply to all the following parameters, unless otherwise specified. V
C
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without
causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the
negative supply.
Note 4: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step
with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.
Note 5: Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can
be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range.
Note 6: See Definition of Terms
Note 7: Human body model, 100pF discharged through 1.5KΩ
Note 8: Parameter tested go no go only for Vth test.
Hold
= 0.01 µF, Logic Reference Pin = 0V, Logic Pin = 4V Deltas required for S-Level product ONLY.
2nd Stage V
Acquisition Time
Input Offset Voltage
Input Bias Current
Parameters
Parameter
Parameter
OS
D
= (T
(Continued)
+V
+V
+V
+V
Delta V
C
Delta V
C
+V
+V
JMAX
Hold
Hold
CC
CC
CC
CC
CC
CC
− T
= 3.5V, -V
= 3V, -V
= 32.5V, -V
= 7V, -V
= 1000pF
= 0.01µF
= 15V, -V
= 15V, -V
OUT
OUT
A
)/θ
Conditions
Conditions
Conditions
JA
= 10V,
= 10V,
, or the number given in the Absolute Maximum Ratings, whichever is lower. .
CC
CC
CC
CC
CC
CC
= -7V
= -3V
6
CC
= -15V
= -15V
CC
= -32.5V
= -3.5V
=
=
±
±
15V, R
15V, R
L
L
= 10KΩ, V
= 10KΩ, V
Notes
Notes
Notes
JMAX
, θ
JA
, and the ambient temperature, T
IN
IN
= 0V, C
CC
Min
Min
Min
-0.5
-2.5
-35
-50
-35
-50
-35
-50
-35
-50
= 0V, C
=
±
15V, R
Max
Max
Max
+35
+50
+35
+50
+35
+50
+35
+50
6.0
0.5
2.5
Hold
25
HOLD
= 0.01 µF, Logic Refer-
= 0.01 µF, Logic Ref-
L
= 10KΩ, V
Unit
Unit
Unit
mV
mV
mV
mV
mV
mV
mV
mV
mV
µS
µS
nA
A
. The maximum
IN
groups
groups
groups
= 0V,
Sub-
Sub-
Sub-
2, 3
2, 3
2, 3
2, 3
1
1
1
1
4
4
1
1