AD1847JP Analog Devices Inc, AD1847JP Datasheet - Page 20

• Manufacturer Part Number: AD1847JP
• Manufacturer: Analog Devices Inc

Specifications of AD1847JP

• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PLCC
• Lead Free Status / RoHS Status: Not Compliant

AD1847
Control Register Mapping Summary
A detailed map of the control register bit assignments is summa-
rized for reference in Figure 9.
Daisy-Chained Multiple Codecs
Multiple AD1847s can be configured in a daisy-chain system
with a single master Codec and one or more slave Codecs.
Codecs in a daisy-chained configuration are synchronized at the
sample level.
The master and slave AD1847s should be powered-up together.
If this is not possible, the slave(s) should power-up before the
master Codec, such that the slave(s) are ready when the master
starts to drive the serial interface, and a serial data frame sync
(SDFS) can synchronize the master and slave(s).
The sample rate for the master and slave(s) should be pro-
grammed together. If this is not possible, the slave(s) should be
programmed before the master AD1847. A slave AD1847 enters
a time-out period after a new sample rate has been selected.
During this time-out period, a slave will ignore any activity on
the SDFS signal (i.e., frame syncs). There is no software means
to determine when a slave has exited from this time-out period
and is ready to respond to frame syncs. However, as long as the
AD1847 master is driving the serial interface, a frame sync will
not occur before the slave Codec(s) are ready.
Note that the time slots for all slave AD1847s must be assigned
to those slots which immediately follow the time slots consumed
by the master AD1847 so that the TSO (Time Slot Output)/TSI
(Time Slot Input) signaling operates properly. For example, in a
2-wire system with one master and one slave, the time slot as-
signment should be 0, 1, 2 (16, 17, 18) for the master AD1847,
and 3, 4, 5 (19, 20, 21) for the slave AD1847.
IA3:0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
XCTL1
Data 7
DMA5
LMX1
RMX1
LMX2
RMX2
LDM
RDM
LSS1
RSS1
inval
inval
inval
FRS
res
res
XCTL0
TSSEL
Data 6
DMA4
LSS0
RSS0
FMT
inval
inval
inval
res
res
res
res
res
res
res
CLKTS
Data 5
DMA3
LDA5
RDA5
inval
inval
inval
C/L
res
res
res
res
res
res
res
res
Figure 9. Register Map Summary
LX1G4
RX1G4
LX2G4
RX2G4
DMA2
Data 4
LDA4
RDA4
inval
inval
inval
S/M
res
res
res
res
res
–20–
LX1G3
RX1G3
LX2G3
RX2G3
Data 3
DMA1
LDA3
RDA3
ACAL
LIG3
RIG3
CFS2
inval
inval
inval
Figure 10 illustrates the connection between master and slave(s)
in a daisy-chained, multiple Codec system. Note that the TSI
pin of the master Codec should be tied to digital ground. The
XTAL1I pin of the slaves should be connected to digital
ground, and XTAL1O pin should be left unconnected, while
the XTAL2I pin should be connected to the CLKOUT pin of
the AD1847 master, and the XTAL2O pin generates a driven
version of the CLKOUT signal applied to the XTAL2I pin.
INITIALIZATION AND PROCEDURES
A total reset of the AD1847 is defined as any event which
requires both the digital and analog section of the AD1847 to
return to a known and stable state. Total reset mode, as well as
power down, occurs when the PWRDOWN pin of the AD1847
has been asserted low for minimum power consumption. When
the PWRDOWN signal is deasserted, the AD1847 must be cali-
brated by setting the ACAL bit and exiting from the Mode
Change Enable (MCE) state.
The reset occurs, and only resets the digital section of the
AD1847, when the RESET pin of the AD1847 has been as-
serted LO to initialize all registers to known values. See the reg-
ister definitions for the exact values initialized. The register reset
defaults include TSSEL = 0 (1-wire system) and FRS = 0
(32 slots per frame). If the target application requires a 2-wire
system design or 16 slots per frame, the AD1847 can be
bootstrapped into these configurations.
res
res
Reset and Power Down
LX1G2
RX1G2
LX2G2
RX2G2
Data 2
DMA0
LDA2
RDA2
LIG2
RIG2
CFS1
inval
inval
inval
res
res
res
LX1G1
RX1G1
LX2G1
RX2G1
Data 1
LDA1
RDA1
LIG1
RIG1
CFS0
inval
inval
inval
res
res
res
res
LX1G0
RX1G0
LX2G0
RX2G0
Data 0
LDA0
RDA0
LIG0
RIG0
DME
PEN
inval
inval
inval
CSL
res
res
Index
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
REV. B