92HD81B1C5NLGXYDX8 IDT, Integrated Device Technology Inc, 92HD81B1C5NLGXYDX8 Datasheet - Page 36

• Manufacturer Part Number: 92HD81B1C5NLGXYDX8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 92HD81B1C5NLGXYDX8

• Lead Free Status / RoHS Status: Compliant

92HD81
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
IDT™ CONFIDENTIAL
2.22. Aux Audio Support
2.22.1. General conditions in Aux Audio Mode:
2.22.2. “Playback Path” Port Behavior
See Orderable Part Numbers for which codecs offer this feature.
The codec supports an auxiliary audio mode where analog audio is supported by default after power
is supplied with the HD Audio bus disabled. In this mode, an analog input is routed to one of several
output ports depending on jack presence detection.
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Port F (Aux Audio In) input is routed to Port D (“internal speakers”), Ports A&B (system headphone
ports), and Port E (Aux Audio Out) through the analog mixer.
HD Audio Link is off (RST# is 0, active, and BitClk is 0, inactive. CODEC does not need to mon-
itor BitClk to enter/exit this mode but must not depend on BitClk to operate.)
HD Audio CODEC analog and digital supplies are active.
Port A may be an optional headphone jack (Normal and Aux Audio Mode) or an internal micro-
phone port (Normal Mode only / 92HD81 only)
Port B connects to the system headphone jack.
Port D connects to the internal speakers.
Port E is AUX Audio out
Port F is AUX Audio In
The internal digital microphone clock is controlled by a source external to the CODEC and the
CODEC will use the DMIC_CLK pin as a clock input. The DMIC0 input is used to process 1 or 2
digital microphone inputs. The expected clock is 3.072MHz.
EAPD is used to control the power state of the mixer, BTL amplifier, and headphone amplifiers.
The amplifiers are off if EAPD is held low.
Internal circuitry will delay enabling (change power state, un-mute, etc.) the output amplifiers a
sufficient amount of time after the application of power or EAPD=1 to prevent pops.
Internal circuitry will orchestrate power down (EAPD = 0) to prevent pops.
EAPD must be forced low before removing power.
ECR15b considerations: Clock Stop OK or similar communication will be used to prevent prob-
lems when an OS driver attempts to put the HD Audio bus controller into D3 to save power. The
bus must not be placed into reset with the clock stopped or unless EAPD is forced low or D3cold
has been set. The Enable bit in the Aux Audio vendor specific verb is provided so firmware or
other software can disable Aux Audio support and allow stopping the HD Audio bus when an OS
is in an active state. The default value of this bit is determined by a bond option and may be
determined by reading the device ID. This bit only returns to its default value when a power on
reset event is generated.
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92HD81