ADAV803AST Analog Devices Inc, ADAV803AST Datasheet
ADAV803AST
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ADAV803AST Summary of contents
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... Device control via I C-compatible serial port 64-lead LQFP package GENERAL DESCRIPTION The ADAV803 is a stereo audio codec intended for applications such as DVD or CD recorders that require high performance and flexible, cost-effective playback and record functionality. The ADAV803 features Analog Devices, Inc. proprietary, high performance converter cores to provide record (ADC), playback (DAC), and format conversion (SRC single chip ...
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ADAV803 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Test Conditions............................................................................. 3 ADAV803 Specifications ............................................................. 3 Timing Specifications .................................................................. 7 Temperature Range ...................................................................... 7 Absolute ...
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SPECIFICATIONS TEST CONDITIONS Test conditions, unless otherwise noted. Table 1. Test Parameter Supply Voltage Analog Digital Ambient Temperature Master Clock (MCLKI) Measurement Bandwidth Word Width (All Converters) Load Capacitance on Digital Outputs ADC Input Frequency DAC Output Frequency Digital Input ...
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ADAV803 Parameter Crosstalk (EIAJ Method) Volume Control Step Size (256 Steps) Maximum Volume Attenuation Mute Attenuation Group Delay kHz kHz S ADC LOW-PASS DIGITAL DECIMATION FILTER 1 CHARACTERISTICS Pass-Band Frequency Stop-Band Frequency Stop-Band ...
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Parameter Crosstalk (EIAJ Method) Phase Deviation Mute Attenuation Volume Control Step Size (256 Steps) Group Delay 48 kHz 96 kHz 192 kHz DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS Pass-Band Frequency Stop-Band Frequency Stop-Band Attenuation Pass-Band Ripple PLL SECTION Master Clock ...
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ADAV803 Parameter POWER Supplies Voltage, AVDD Voltage, DVDD Voltage, ODVDD Operating Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current Power-Down Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current Power Supply Rejection Signal ...
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TIMING SPECIFICATIONS Timing specifications are guaranteed over the full temperature and supply range. Table 3. Parameter Symbol MASTER CLOCK AND RESET MCLKI Frequency f MCLK XIN Frequency f XIN RESET Low t RESET PORT SCL Clock Frequency ...
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ADAV803 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating DVDD to DGND and ODVDD 4 DGND AVDD to AGND 4.6 V Digital Inputs DGND − 0 DVDD + 0.3 V Analog ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DIR_GND DIR_VDD ZEROL/INT CONNECT Table 6. Pin Function Descriptions Pin No. Mnemonic I/O Description 1 VINR I Analog Audio Input, Right Channel. 2 VINL I Analog Audio Input, Left Channel. 3 AGND ...
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ADAV803 Pin No. Mnemonic I/O Description 27 OAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Output Port. 28 OAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Output Port. 29 OAUXSDATA O Data Output of Auxiliary Digital Output Port. 30 IAUXLRCLK ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –50 –100 –150 0 0.5 1.0 FREQUENCY (Normalized to f Figure 3. ADC Composite Filter Response 5 0 –5 –10 –15 –20 –25 – FREQUENCY (Hz) Figure 4. ADC High-Pass Filter Response, f ...
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ADAV803 0 –50 –100 –150 0 192 384 FREQUENCY (kHz) Figure 9. DAC Composite Filter Response, 96 kHz 0 –50 –100 –150 FREQUENCY (kHz) Figure 10. DAC Pass-Band Filter Response, 96 kHz 0.10 0.05 0 –0.05 –0.10 ...
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FREQUENCY (kHz) Figure 15. DAC Dynamic Range kHz S 0 –20 –40 –60 –80 –100 –120 –140 –160 0 2 ...
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ADAV803 0 –20 –40 –60 –80 –100 –120 –140 –160 FREQUENCY (kHz) Figure 21. ADC Dynamic Range, f DNR = 102dB (A-WEIGHTED) –100 –120 –140 –160 kHz S Rev ...
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FUNCTIONAL DESCRIPTION ADC SECTION The ADAV803’s ADC section is implemented using a second- order multibit (5 bits) Σ-Δ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clock = 128 × one-quarter ...
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ADAV803 Automatic Level Control (ALC) The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal at the input pins causes the ...
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Selecting a Sample Rate The output sample rate of the ADC is always ADC MCLK/256, as shown in Figure 23. By default, the ADC modulator runs at ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz, the ADC modulator should ...
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ADAV803 DAC SECTION The ADAV803 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375 dB per step. The DAC can receive data ...
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SAMPLE RATE CONVERTER (SRC) FUNCTIONAL OVERVIEW During asynchronous sample rate conversion, data can be converted at the same sample rate or at different sample rates. The simplest approach to an asynchronous sample rate conversion is to use a zero-order hold ...
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ADAV803 The worst-case images can be computed from the zero-order hold frequency response: Maximum Image = sin(π × F/f S_INTERP where the frequency of the worst-case image that would × f ± f /2. S_IN ...
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The maximum decimation rate can be calculated from the RAM word depth and the group delay as (512 − 16)/64 taps ...
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ADAV803 PLL SECTION The ADAV803 features a dual PLL configuration to generate independent system clocks for asynchronous operation. Figure 37 shows the block diagram of the PLL section. The PLL generates the internal and system clocks from a 27 MHz ...
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S/PDIF TRANSMITTER AND RECEIVER The ADAV803 contains an integrated S/PDIF transmitter and receiver. The transmitter consists of a single output pin, DITOUT, on which the biphase encoded data ...
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ADAV803 Serial Digital Audio Transmission Standards The ADAV803 can receive and transmit S/PDIF, AES/EBU, and IEC-958 serial streams. S/PDIF is a consumer audio standard, and AES/EBU is a professional audio standard. IEC-958 has both consumer and professional definitions. This data ...
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Table 10. Professional Audio Standard Data Bits 1 Address Sample Lock Emphasis Frequency User Bit Management Alignment Source Word Level Length Channel Identification N + ...
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ADAV803 The size of the user bit buffer can be set by programming the RxBCONF0 bit in the receiver buffer configuration register, as shown in Table 11. Table 11. RxBCONF3 Functionality RxBCONF0 Receiver User Bit Buffer Size 0 384 bits ...
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Table 15. Transmitter User Bit Buffer Size TxBCONF0 Buffer Size 0 384 bits with Preamble Z as the start of the block. 1 768 bits with Preamble Z as the start of the block. By using sticky bits and interrupts, ...
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ADAV803 REG 0x76 BITS[4:2] ADC OUTPUT f DIR PLL(512 × ) MCLK S f DIR PLL(256 × PLLINT1 PLLINT2 ICLK1 MCLKI ICLK2 XIN PLL CLOCK REG 0x76 BITS[7:5] DAC f DIR PLL(512 × ) MCLK S f DIR ...
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Datapath The ADAV803 features a digital input/output switching/ multiplexing matrix that gives flexibility to the range of possible input and output connections. Digital input ports include playback and auxiliary input (both 3-wire digital), and S/PDIF (single-wire to the on-chip receiver). ...
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ADAV803 INTERFACE CONTROL The ADAV803 has a dedicated control port to allow the internal registers of the ADAV803 to be accessed. Each of the internal registers is eight bits wide. Where bits are described as reserved (RES), these bits should ...
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SCL 0 SDA 0 START BY MASTER SCL (CONTINUED) SDA (CONTINUED) REPEATED START BY MASTER BLOCK READS AND WRITES The ADAV803 provides the user with the ability to write to or read from a block of registers ...
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ADAV803 REGISTER DESCRIPTIONS SRC and Clock Control—Address 0000000 (0x00) Table 17. SRC and Clock Control Register Bit Map SRCDIV1 SRCDIV0 CLK2DIV1 Table 18. SRC and Clock Control Register Bit Descriptions Bit Name Description SRCDIV[1:0] Divides the SRC ...
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Playback Port Control—Address 0000100 (0x04) Table 21. Playback Port Control Register Bit Map Reserved Reserved Reserved Table 22. Playback Port Control Register Bit Descriptions Bit Name Description CLKSRC[1:0] Selects the clock source for generating the ILRCLK and ...
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ADAV803 Record Port Control—Address 0000110 (0x06) Table 25. Record Port Control Register Bit Map Reserved Reserved CLKSRC1 Table 26. Record Port Control Register Bit Descriptions Bit Name Description CLKSRC[1:0] Selects the clock source for generating the OLRCLK ...
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Group Delay and Mute—Address 0001000 (0x08) Table 29. Group Delay and Mute Register Bit Map MUTE_SRC GRPDLY6 GRPDLY5 Table 30. Group Delay and Mute Register Bit Descriptions Bit Name Description MUTE_SRC Soft-mutes the output of the sample ...
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ADAV803 Receiver Configuration 2—Address 0001010 (0x0A) Table 33. Receiver Configuration 2 Register Bit Map RxMUTE SP_PLL SP_PLL_ SEL1 Table 34. Receiver Configuration 2 Register Bit Descriptions Bit Name Description RxMUTE Hard-mutes the audio output for the AES3/S/PDIF ...
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Receiver Buffer Configuration—Address 0001011 (0x0B) Table 35. Receiver Buffer Configuration Register Bit Map Reserved Reserved RxBCONF5 Table 36. Receiver Buffer Configuration Register Bit Descriptions Bit Name Description RxBCONF5 If the user bits are formatted according to the ...
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ADAV803 Transmitter Buffer Configuration—Address 0001101 (0x0D) Table 39. Transmitter Buffer Configuration Register Bit Map IU_Zeros3 IU_Zeros2 IU_Zeros1 Table 40. Transmitter Buffer Configuration Register Bit Descriptions Bit Name Description IU_Zeros[3:0] Determines the number of zeros to be stuffed ...
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Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F) Table 43. Transmitter Message Zeros Most Significant Byte Register Bit Map MSBZeros7 MSBZeros6 MSBZeros5 Table 44. Transmitter Message Zeros Most Significant Byte Register Bit Description Bit Name Description MSBZeros[7:0] ...
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ADAV803 Sample Rate Ratio LSB—Address 0010011 (0x13) Table 51. Sample Rate Ratio LSB Register (Read-Only) Bit Map SRCRATIO07 SRCRATIO06 SRCRATIO05 Table 52. Sample Rate Ratio LSB Register (Read-Only) Bit Descriptions Bit Name Description SRCRATIO[7:0] Eight least significant ...
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Receiver Error—Address 0011000 (0x18) Table 61. Receiver Error Register (Read-Only) Bit Map RxValidity Emphasis NonAudio Table 62. Receiver Error Register (Read-Only) Bit Descriptions Bit Name Description RxValidity This is the VALIDITY bit in the AES3 received stream. ...
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ADAV803 Sample Rate Converter Error—Address 0011010 (0x1A) Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map Reserved Reserved Reserved Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions Bit Name Description TOO_SLOW This bit is ...
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Interrupt Status—Address 0011100 (0x1C) Table 69. Interrupt Status Register Bit Map SRCError TxCSTINT TxUBINT Table 70. Interrupt Status Register Bit Descriptions Bit Name Description SRCError This bit is set if one of the sample rate converter interrupts ...
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ADAV803 Mute and De-Emphasis—Address 0011110 (0x1E) Table 73. Mute and De-Emphasis Register Bit Map Reserved Reserved TxMUTE Table 74. Mute and De-Emphasis Register Bit Descriptions Bit Name Description TxMUTE Mutes the AES3/S/PDIF transmitter Transmitter is ...
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Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50) Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map RxUBADDR7 RxUBADDR6 RxUBADDR5 Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions Bit Name Description ...
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ADAV803 Q Subcode Buffer—Address 0x55 to Address 0x5E Table 91. Q Subcode Buffer Bit Map Address Bit 7 Bit 6 0x55 Address Address 0x56 Track Track number number 0x57 Index Index 0x58 Minute Minute 0x59 Second Second 0x5A Frame Frame ...
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Datapath Control Register 2—Address 1100011 (0x63) Table 94. Datapath Control Register 2 Bit Map Reserved Reserved DAC2 Table 95. Datapath Control Register 2 Bit Descriptions Bit Name Description DAC[2:0] Datapath source select for DAC ADC. ...
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ADAV803 DAC Control Register 2—Address 1100101 (0x65) Table 98. DAC Control Register 2 Bit Map Reserved Reserved DMCLK1 Table 99. DAC Control Register 2 Bit Descriptions Bit Name Description DMCLK[1:0] DAC MCLK divider MCLK. 01 ...
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DAC Control Register 4—Address 1100111 (0x67) Table 102. DAC Control Register 4 Bit Map Reserved INTRPT ZEROSEL1 Table 103. DAC Control Register 4 Bit Descriptions Bit Name Description INTRPT This bit selects the functionality of the ZEROL/INT ...
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ADAV803 DAC Right Peak Volume—Address 1101011 (0x6B) Table 110. DAC Right Peak Volume Register Bit Map Reserved Reserved DRP5 Table 111. DAC Right Peak Volume Register Bit Descriptions Bit Name Description DRP[5:0] DAC right channel peak volume ...
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ADC Control Register 1—Address 1101110 (0x6E) Table 116. ADC Control Register 1 Bit Map AMC HPF PWRDWN Table 117. ADC Control Register 1 Bit Descriptions Bit Name Description AMC ADC modulator clock ADC MCLK/2 (128 ...
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ADAV803 ADC Left Volume—Address 1110000 (0x70) Table 120. ADC Left Volume Register Bit Map AVOLL7 AVOLL6 AVOLL5 Table 121. ADC Left Volume Register Bit Descriptions Bit Name Description AVOLL[7:0] ADC left channel volume control. 1111111 = 1.0 ...
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PLL Control Register 1—Address 1110100 (0x74) Table 128. PLL Control Register 1 Bit Map DIRIN_CLK1 DIRIN_CLK0 MCLKODIV Table 129. PLL Control Register 1 Bit Descriptions Bit Name Description DIRIN_CLK[1:0] Recovered S/PDIF clock sent to SYSCLK3 ...
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ADAV803 PLL Control Register 2—Address 1110101 (0x75) Table 130. PLL Control Register 2 Bit Map FS2_1 FS2_0 SEL2 Table 131. PLL Control Register 2 Bit Descriptions Bit Name Description FS2_[1:0] Sample rate select for PLL2 ...
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Internal Clocking Control Register 1—Address 1110110 (0x76) Table 132. Internal Clocking Control Register 1 Bit Map DCLK2 DCLK1 DCLK0 Table 133. Internal Clocking Control Register 1 Bit Descriptions Bit Name Description DCLK[2:0] DAC clock source select. 000 ...
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ADAV803 PLL Clock Source Register—Address 1111000 (0x78) Table 136. PLL Clock Source Register Bit Map PLL2_Source PLL1_Source Reserved Table 137. PLL Clock Source Register Bit Descriptions Bit Name Description PLL2_Source Selects the clock source for PLL2. 0 ...
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ALC Control Register 1—Address 1111011 (0x7B) Table 140. ALC Control Register 1 Bit Map FSSEL1 FSSEL0 GAINCNTR1 Table 141. ALC Control Register 1 Bit Descriptions Bit Name Description FSSEL[1:0] These bits should equal the sample rate of ...
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ADAV803 ALC Control Register 2— Address = 1111100 (0x7C) Table 142. ALC Control Register 2 Bit Map Reserved RECTH1 RECTH0 Table 143. ALC Control Register 2 Bit Descriptions Bit Name Description RECTH[1:0] Recovery threshold −2 ...
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LAYOUT CONSIDERATIONS Getting the best performance from the ADAV803 requires a careful layout of the printed circuit board (PCB). Using separate analog and digital ground planes is recommended, because these give the currents a low resistance path back to the ...
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... ROTATED 90° CCW ORDERING GUIDE Temperature Model Range 1 ADAV803ASTZ −40°C to +85°C ADAV803ASTZ-REEL 1 −40°C to +85°C 1 EVAL-ADAV803EBZ RoHS Compliant Part. Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent Rights to use these components in an I² ...