IDT92HD81B1X5NLGXYCX8 IDT, Integrated Device Technology Inc, IDT92HD81B1X5NLGXYCX8 Datasheet - Page 15

• Manufacturer Part Number: IDT92HD81B1X5NLGXYCX8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT92HD81B1X5NLGXYCX8

• Lead Free Status / RoHS Status: Compliant

92HD81
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
IDT™ CONFIDENTIAL
2.1.1.
2.1.2.
2.1.3.
Port Characteristics
Universal (Bi-directional) jacks are supported on ports C (YD and UA revisions only), E, and F. Port
A is birdirectional also. Ports A and B are designed to drive 32 ohm (nominal) headphones or a 10K
(nominal) load. Line Level outputs are intended to drive an external 10K load (nominal) and an on
board shunt resistor of 20-47K (nominal). However, applications may support load impedances of 5K
ohms and above. Input ports are 50K (nominal) at the pin.
DAC full scale outputs and intended full scale input levels are 1V rms at 5V. Line output ports and
Headphone output ports on the 92HD81 codec may be configured for +3dBV full scale output levels
by using a vendor specific verb.
Output ports are always on to prevent pops/clicks associated with charging and discharging output
coupling capacitors. This maintains proper bias on output coupling caps even in power state D3 as
long as AVDD is available. Unused ports should be left unconnected. When updating existing
designs to use the 92HD81 codec, ensure that there are no conflicts between the output ports on the
92HD81 codec and existing circuitry.
Vref_Out
Ports C & A support Vref_Out pins for biasing electret cartridge microphones. Settings of 80%
AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a pin widget control with a
reserved or unsupported value will cause the associated Vref_Out pin to assume a Hi-Z state and
the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when read.
Jack Detect
Plugs inserted to a jack on Ports A, B, C & SPDIFOUT0 are detected using SENSE_A. Plugs
inserted to a jack on Ports E,F, DMIC0, & SPDIFOUT1 are detected using SENSE_B. Per ECR15-B,
the detection circuit operates when the CODEC is in D0 - D3 and can also operate if both the
CODEC and Controller are in D3 (no bus clock.) Jack detection requires that all supplies (analog
and digital) are active and stable. When AVDD is not present, the value reported in the pin widget is
invalid.
AFG Power State
D0-D2
D3
D3cold
D4
D5
Input Enable
1
1
0
0
-
-
-
-
-
Table 2. Analog Output Port Behavior
Output Enable
15
1
0
1
0
0
1
-
-
-
Port Behavior
Active - Port enabled as input
Active - Port enabled as output
Inactive -port is powered on (low output impedance) but
drives silence only.
Inactive (lower power) - Port keeps output coupling caps
charged if port uses caps.
Low power state. If enabled, Beep will output from the port
Inactive (lower power) - Port keeps output coupling caps
charged if port uses caps.
Inactive (lower power) - Port keeps output coupling caps
charged if port uses caps.
Off - Charge on coupling caps (if used) will not be
maintained.
Not allowed. Port is active as output. Input path is
mute.
V 0.987 11/09
92HD81