CY7C68000-48BAC Cypress Semiconductor Corp, CY7C68000-48BAC Datasheet - Page 5

• Manufacturer Part Number: CY7C68000-48BAC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68000-48BAC

• Number Of Transceivers: 1
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

Mode 0 allows the transceiver to operate with normal USB data decoding and encoding.
Mode 1 allows the transceiver logic to support a soft disconnect feature which three-states both the HS and FS transmitters, and
removes any termination from the USB, making it appear to an upstream port that the device has been disconnected from the bus.
Mode 2 disables Bit Stuff and NRZI encoding logic so 1s loaded from the data bus becomes Js on the DPLUS/DMINUS lines
and 0s become Ks.
4.0
The CY7C68000 does not require external resistors for USB data line impedance termination or an external pull up resistor on
the DPLUS line. These resistors are incorporated into the part. They are factory trimmed to meet the requirements of USB 2.0.
Incorporating these resistors also reduces the pin count on the part.
5.0
The following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are
available in the 48- and 56-pin packages.
The 48-pin package is the lowest-cost version and provides an 8-bit, 60-MHz interface.
The 56-pin package is the full version, offering an 8-bit (60-MHz) or 16-bit (30-MHz) bus interface. The two signals required for
16-bit operation are ValidH and DataBus16_8, and are present only in the 56-pin version.
Document #: 38-08016 Rev. *C
OpMode[1:0]
DPLUS/DMINUS Impedance Termination
Pin Assignments
00
01
10
11
LINESTATE1
LINESTATE0
OPMODE1
RXVALID
AGND
AGND
GND
CLK
C1
G1
A1
B1
D1
E1
F1
H1
Mode
0
1
2
3
Figure 5-1. CY7C68000 48-pin FBGA Pin Assignment
RXACTIVE
RXERROR
Reserved
Reserved
DMINUS
Normal operation
Non-driving
Disable Bit Stuffing and NRZI encoding
Reserved
GND
GND
GND
C2
G2
H2
A2
B2
D2
E2
F2
TERMSELECT
OPMODE0
Reserved
DPLUS
V
V
48-pin FBGA
C3
G3
A3
B3
D3
E3
D7
D6
F3
H3
CC
CC
XCVRSELECT
Reserved
Reserved
GND
C4
G4
A4
B4
D4
E4
H4
V
F4
NC
D5
D4
CC
Description
SUSPEND
XTALOUT
Reserved
RESET
V
V
C5
G5
A5
B5
D5
E5
F5
H5
D3
D2
CC
CC
TXREADY
Reserved
TXVALID
XTALIN
AV
AV
C6
G6
A6
D6
E6
H6
B6
F6
D1
D0
CC
CC
CY7C68000
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