SC28L91A1A-S NXP Semiconductors, SC28L91A1A-S Datasheet - Page 30

• Manufacturer Part Number: SC28L91A1A-S
• Manufacturer: NXP Semiconductors

Specifications of SC28L91A1A-S

• Transmit Fifo: 16Byte
• Receive Fifo: 16Byte
• Transmitter And Receiver Fifo Counter: Yes
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

transmitter as described in CSR. Baud rate generator characteristics
Philips Semiconductors
OPR Output Port Register
The output pins (OP pins) drive the compliment of the data in this register as controlled by SOPR and ROPR.
ACR Auxiliary Control Register
ACR—Auxiliary Control Register
ACR[7]—Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG (see Table 5).
The selected set of rates is available for use by the receiver and
are given in Table 6.
ACR[6:4]—Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 7
ACR[3:0]—IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR [7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR [7], which results in
the generation of an interrupt output if IMR [7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR [7].
IPCR Input Port change Register
IPCR[7:4]—IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR [7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
2004 Oct 21
Addr
N/A
N/A
Addr
ACR
0x04
Addr
IPCR
0x04
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
Bit 7
Delta IP3
0 = no change 0 = no change 0 = no change 0 = no change
1 = change
Bit 7
BRG SET
Select
0 = set 1
1 = set 2
Bit 7
OP 7
0 = Pin High
1 = Pin Low
BIT 6
Delta IP3
1 = change
BIT 6
Counter Timer Mode
Mode and clock sour select
See table 7
BIT 6
OP 6
0 = Pin High
1 = Pin Low
BIT 5
Delta IP3
1 = change
BIT 5
OP 5
0 = Pin High
1 = Pin Low
BIT 5
BIT 4
Delta IP3
1 = change
BIT 4
OP 4
0 = Pin High
1 = Pin Low
BIT 4
30
1. The timer mode generates a square wave
information is unlatched and reflects the state of the input pins at the
Table 7. ACR 6:4 field definition
NOTE:
IPCR[3:0]—IP3, IP2, IP1, IP0 Change-of-State
These bits provide the current state of the respective inputs. The
time the IPCR is read.
ACR
6:4
000
001
010
011
100
101
110
111
BIT 3
IP 3
0 = low
1 = High
BIT 3
Delta IP3 int
enable
0 = off
1 = enabled
BIT 3
OP 3
0 = Pin High
1 = Pin Low
MODE
Counter
Counter
Counter
Timer
Timer
Timer
Timer
BIT 2
IP 2
0 = low
1 = High
BIT 2
OP 2
0 = Pin High
1 = Pin Low
BIT 2
Delta IP3 int
enable
0 = off
1 = enabled
CLOCK SOURCE
External (IP2)
TxC – 1X clock of transmitter
reserved
Crystal or X1/CLK clock divided by 16
External (IP2)
External (IP2) divided by 16
Crystal or external clock (X1/CLK)
Crystal or external clock (X1/CLK) divided
by 16
BIT 1
IP 1
0 = low
1 = High
BIT 1
Delta IP3 int
enable
0 = off
1 = enabled
BIT 1
OP 1
0 = Pin High
1 = Pin Low
SC28L91
Product data sheet
BIT 0
IP 0
0 = low
1 = High
BIT 0
Delta IP3 int
enable
0 = off
1 = enabled
BIT 0
OP 0
0 = Pin High
1 = Pin Low